SH7616 datasheet(209/935 Pages) RENESAS

209 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 183 of 906

REJ09B0292-0200

5.3.26

Vector Number Setting Register T (VCRT)

Vector number setting register T (VCRT) is a 16-bit read/write register that sets the serial I/O 2

(SIO2) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0–

127).

VCRT is initialized to H'0000 by a reset. It is not initialized in standby mode.

Bit:

—

RER2V6 RER2V5 RER2V4 RER2V3 RER2V2 RER2V1 RER2V0

Initial value:

00000000

R/W:

R/W

Bit:

76543210

—

TER2V6 TER2V5 TER2V4 TER2V3 TER2V2 TER2V1 TER2V0

Initial value:

00000000

R/W:

R/W

Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 14 to 8—Serial I/O 2 (SIO2) Receive Overrun Error Interrupt Vector Number 6 to 0

(RER2V6–RER2V0): These bits set the vector number for the serial I/O 2 (SIO2) receive overrun

error interrupt. There are seven bits, so the value can be set between 0 and 127.

Bits 6 to 0—Serial I/O 2 (SIO2) Transmit Underrun Error Interrupt Vector Number 6 to 0

(TER2V6–TER2V0): These bits set the vector number for the serial I/O 2 (SIO2) transmit

underrun error interrupt. There are seven bits, so the value can be set between 0 and 127.

SH7616 Datasheet(PDF) 209 Page - Renesas Technology Corp