SH7616 datasheet(313/935 Pages) RENESAS

313 / 935 page

Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 287 of 906

REJ09B0292-0200

7.4.2

Wait State Control

The number of wait states inserted into ordinary space access states can be controlled using the

WCR1, WCR2, BCR1 and BCR3 register settings. When the Wn1 and Wn0 wait specification bits

in WCR1, WCR2 for the given CS space are 01 or 10, software waits are inserted according to the

wait specification. When Wn1 and Wn0 are 11, wait cycles are inserted according to the long wait

specification bit AnLW in BCR1, BCR3. The long wait specification in BCR1, BCR3 can be

made independently for CS0, CS1 and CS4 spaces, but the same value must be specified for CS2

and CS3 spaces. All WCR1 specifications are independent. By means of WCR1, WCR2, BCR1,

and BCR3, a Tw cycle is inserted as a wait cycle as long as the number of specified cycles at the

wait timing for ordinary access space shown in figure 7.16. The names of the control bits that

specify Tw for each CS space are shown in table 7.5.

CKIO

A24–A0

CSn

RD/

D31–D0

WEn

D31–D0

DACKn*

Read

Write

Note: * DACKn waveform when active–low is specified.

Figure 7.16 Wait Timing of Ordinary Space Access (Software Wait Only)

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