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SH7616 Datasheet(PDF) 309 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 309 Page - Renesas Technology Corp |
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309 / 935 page ![]() Section 7 Bus State Controller (BSC) Rev. 2.00 Mar 09, 2006 page 283 of 906 REJ09B0292-0200 T1 T2 CKIO A24–A0 CSn RD/ WR RD D31–D0 WEn D31–D0 BS DACKn* Read Write Note: * DACKn waveform when active-low is specified. Figure 7.11 Basic Timing of Ordinary Space Access When making a word or longword access with an 8-bit bus width, or a longword access with a 16- bit bus width, the bus state controller performs multiple accesses. When clock ratio I φ : Eφ is other than 1 : 1, the basic timing shown in figure 7.11 is repeated, but when clock ratio I φ : Eφ is 1 : 1, burst access with no CSn negate period is performed as shown in figure 7.12. |
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