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SH7616 Datasheet(PDF) 314 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 314 Page - Renesas Technology Corp |
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314 / 935 page  Section 7 Bus State Controller (BSC) Rev. 2.00 Mar 09, 2006 page 288 of 906 REJ09B0292-0200 Table 7.5 CSn Spaces and Tw Specification Bits BCR3 BCR1 WCR1 WCR2 Tw CS0 A0LW2 A0LW1 A0LW0 W01 W00 — — 0–14 CS1 A1LW2 A1LW1 A2LW0 W11 W10 — — 0–14 CS2 AHLW2 AHLW1 AHLW0 W21 W20 — — 0–14 CS3 AHLW2 AHLW1 AHLW0 W31 W30 — — 0–14 CS4 A4LW2 A4LW1 A4LW0 — — W41 W40 0–14 When a wait is specified by software using WCR1 and WCR2 (Wn1, Wn0), and the external wait mask bit (AnWM) is cleared to 0 in WCR2, the wait input WAIT signal from outside is sampled. Figure 7.17 shows WAIT signal sampling. A 2-cycle wait is specified as a software wait. The sampling is performed when the Tw state shifts to the T2 state, so there is no effect even when the WAIT signal is asserted in the T1 cycle or the first Tw cycle. The WAIT signal is sampled at the clock fall. |
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