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SH7727 Datasheet(PDF) 104 Page - Renesas Technology Corp

Part # SH7727
Description  Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
PDF  1109 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7727 Datasheet(HTML) 104 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 5.00 Dec 12, 2005 page 32 of 1034
REJ09B0254-0500
When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the
register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored to the X or Y memory by
this operation, but other registers cannot be stored.
There are some rules to access SR by STC/LDC instruction.
1. When DSP is disabled, same as SH-3 behavior
2. When SDP supervisor mode, same as supervisor mode
3. In User DSP mode, SR can be read by STC instruction
4. In User DSP mode, LDC to SR is allowed but no DSP related bits are protected from write.
Table 2.2 shows detail behavior under each SH3-DSP mode.



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