SH7727 datasheet(108/1109 Pages) RENESAS

108 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 36 of 1034

REJ09B0254-0500

Table 2.5

DSR Register Bits

Bit

Name (Abbreviation)

Function

31–8

Reserved bits

0: Always read out; always use 0 as a write value

Signed greater than bit

(GT)

Indicates that the operation result is positive

(excepting 0), or that operand 1 is greater than

operand 2

1: Operation result is positive, or operand 1 is greater

Zero bit (Z)

Indicates that the operation result is zero (0), or that

operand 1 is equal to operand 2

1: Operation result is zero (0), or equivalence

Negative bit (N)

Indicates that the operation result is negative, or that

operand 1 is smaller than operand 2

1: Operation result is negative, or operand 1 is

smaller

Overflow bit (V)

Indicates that the operation result has overflowed

1: Operation result has overflowed

3–1

Status selection bits (CS) Designate the mode for selecting the operation result

status set in the DC bit

Do not set either 110 or 111

000: Carry/borrow mode

001: Negative value mode

010: Zero mode

011: Overflow mode

100: Signed greater mode

101: Signed above mode

DSP status bit (DC)

Sets the status of the operation result in the mode

designated by the CS bits

0: Designated mode status not realized (unrealized)

1: Designated mode status realized

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