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SH7727 Datasheet(PDF) 111 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 111 Page - Renesas Technology Corp |
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111 / 1109 page ![]() Section 2 CPU Rev. 5.00 Dec 12, 2005 page 39 of 1034 REJ09B0254-0500 39 S 31 30 0 −28 to +28 − 2−31 39 S 32 31 0 −223 to +223 − 1 39 S S 31 30 16 15 16 15 0 −1 to +1 − 2−15 39 31 16 15 0 S 31 0 −215 to +215 − 1 16 15 31 22 0 −32 to +32 16 15 S 31 21 0 −16 to +16 16 15 S 31 30 0 −1 to +1 − 2−31 S 31 0 −231 to +231 − 1 DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer DSP type logical With guard bits CPU type integer S: Sign bit Longword : Binary point : Does not affect the operations Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) Figure 2.10 Data Format Shift amount for arithmetic shift (PSHA) instruction has 7 bits filed that could represent –64 to +63, however –32 to +32 is the valid number for the operation. Also the shift amount for logical shift operation has 6-bits field, however –16 to +16 is the valid number for the instruction. |
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