SH7727 datasheet(113/1109 Pages) RENESAS

113 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 41 of 1034

REJ09B0254-0500

Table 2.6

Word Data Sign Extension

SH7727 CPU

Description

Example of Other CPU

MOV.W

@(disp,PC),R1

ADD

R1,R0

........

.DATA.W H'1234

Sign-extended to 32 bits, R1

becomes H'00001234, and is

then operated on by the ADD

instruction.

ADD.W

#H'1234,R0

Note: Immediate data is referenced by @(disp,PC).

Load/Store Architecture: Basic operations are executed between registers. In operations

involving memory, data is first loaded into a register (load/store architecture). However, bit

manipulation instructions such as AND are executed directly on memory.

Delayed Branching: Unconditional branch instructions, etc., are executed as delayed branches.

With a delayed branch instruction, the branch is made after execution of the instruction (called the

slot instruction) immediately following the delayed branch instruction. This minimizes disruption

of the pipeline when a branch is made.

With a delayed branch, the actual branch operation occurs after execution of the slot instruction.

However, instruction execution for register updating, etc., excluding the branch operation, is

performed in delayed branch instruction

→ delay slot instruction order. For example, even though

the contents of the register holding the branch destination address are changed in the delay slot,

the branch destination address remains as the register contents prior to the change.

Table 2.7

Delayed Branch Instructions

SH7727 CPU

Description

Example of Other CPU

BRA

TRGET

ADD

R1,R0

ADD is executed before branch to

TRGET.

ADD.W R1,R0

BRA

TRGET

Multiply/Multiply-and-Accumulate Operations: A 16

× 16 → 32 multiply operation is

executed in 1 to 3 states, and a 16

× 16 + 64 → 64 multiply-and-accumulate operation in 2 to 3

states. A 32

× 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-accumulate

operation are each executed in 2 to 5 states.

T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a

conditional branch is performed according to whether the result is True or False. Processing speed

has been improved by keeping the number of instructions that modify the T bit to a minimum.

SH7727 Datasheet(PDF) 113 Page - Renesas Technology Corp

SH7727 Datasheet(HTML) 113 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL