SH7727 datasheet(116/1109 Pages) RENESAS

116 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 44 of 1034

REJ09B0254-0500

2.4

Instruction Formats

2.4.1

CPU Instruction Addressing Modes

The following table shows addressing modes and effective address calculation methods for

instructions executed by the CPU core.

Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

direct

Effective address is register Rn.

(Operand is register Rn contents.)

—

indirect

@Rn

Effective address is register Rn contents.

indirect with

post-

increment

@Rn+

Effective address is register Rn contents. A

constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand.

1/2/4

Rn + 1/2/4

After instruction

execution

Byte:

Rn + 1

→ Rn

Word:

Rn + 2

→ Rn

Longword:

Rn + 4

→ Rn

indirect with

pre-

decrement

@–Rn

Effective address is register Rn contents,

decremented by a constant beforehand: 1 for a

byte operand, 2 for a word operand, 4 for a

longword operand.

1/2/4

− 1/2/4

−

− 1/2/4

Byte:

Rn – 1

→ Rn

Word:

Rn – 2

→ Rn

Longword:

Rn – 4

→ Rn

(Instruction

executed with Rn

after calculation)

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