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SH7727 Datasheet(PDF) 119 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 119 Page - Renesas Technology Corp |
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119 / 1109 page  Section 2 CPU Rev. 5.00 Dec 12, 2005 page 47 of 1034 REJ09B0254-0500 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC-relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC 2 + × disp (sign-extended) PC + disp × 2 PC + disp × 2 disp:12 Effective address is PC with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC 2 + × disp (sign-extended) PC + disp × 2 PC + disp × 2 Rn Effective address is sum of PC and Rn. PC Rn + PC + Rn PC + Rn Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. — #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. — #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. — |
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