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SH7727 Datasheet(PDF) 105 Page - Renesas Technology Corp

Part # SH7727
Description  Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
PDF  1109 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7727 Datasheet(HTML) 105 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 5.00 Dec 12, 2005 page 33 of 1034
REJ09B0254-0500
Table 2.2
Detail Behavior Under Each SH3-DSP Mode
Supervisor
Mode
User Mode
DSP
Supervisor
Mode
DSP User
Mode
Fields
MD = 1 &
DSP = 0
MD = 0 &
DSP = 0
MD = 1 &
DSP = 1
MD = 0 &
DSP = 1
Access to
DSP Related
Bits by
Dedicated
Instruction
Initial Value after
Reset
MD
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
RB
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
BL
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1
RC [11:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
SETRC
instruction
0b000000000000
DSP
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
0
DMX
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
0
DMY
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
0
Q
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
MS: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
I [3:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
1111
RF [1:0]
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: OK
SETRC
instruction
X
S
S: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
TS: OK,
L: OK
S, L: illegal
instruction
S: OK,
L: OK
S: OK,
L: NG
X
(S) STC:
Store SR to Rn, SR
→ Rn
(L) LDC:
Load Rn to SR, Rn
→ SR
OK:
Allowed to STC/LSC operation
Illegal instruction: Treated as illegal instruction, exception should be occurred
NG:
Keep previous value, nothing changed
Third one is single-data transfer instruction, “MOVS.W” and “MOVS.L”. This instruction
accesses any memory location through LDB (figure 2.8). All DSP registers connect to the LDB
and be able to be source and destination register of the data transfer. It has word and longword
access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16
bits (bits 31 to 16) for the DSP registers except A0G and A1G. When data is loaded into a register



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