HD6433713 datasheet(156/324 Pages) RENESAS

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Bits 6 to 3: Reserved bits

Bits 6 to 3 are reserved; they always read 1, and cannot be modified.

Bits 2 to 0: Clock select (TMB2 to TMB0)

Bits 2 to 0 select the clock input to TCB. For external clock counting, either the rising or falling

edge can be selected.

Bit 2

Bit 1

Bit 0

TMB2

TMB1

TMB0

Description

Internal clock:

φ/8192.

(initial value)

Internal clock:

φ/2048.

Internal clock:

φ/512.

Internal clock:

φ/256.

Internal clock:

φ/128.

Internal clock:

φ/32.

Internal clock:

φ/8.

External clock (P10/IRQ0): rising or falling edge.*

Note: * The edge of the external event signal is selected by bit IEG0 in the IRQ edge select

Timer counter B (TCB)

TCB is an 8-bit read-only up-counter, which is incremented by internal or external clock input.

The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode

When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt

request register 2 (IRR2) is set to 1.

TCB is allocated to the same address as timer load register B (TLB).

Upon reset, TCB is initialized to H'00.

Bit

Initial value

Read/Write

TCB7

TCB6

TCB5

TCB4

TCB3

TCB0

TCB2

TCB1

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HD6433713 Datasheet(PDF) 156 Page - Renesas Technology Corp

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