HD6433713 datasheet(157/324 Pages) RENESAS

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Timer load register B (TLB)

TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB).

When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well,

and TCB starts counting up from that value. When TCB overflows during operation in auto-

reload mode, the TLB value is loaded in TCB. Accordingly, overflow periods can be set within

the range of 1 to 256 input clocks.

The same address is allocated to TLB as to TCB.

Upon reset, TLB is initialized to H'00.

8.3.3 Timer Operation

Timer B is an 8-bit multifunction timer. It can be used as an interval timer, an auto-reload timer,

or an event counter. (Event counting requires an input pin setting.)

Timer B operation modes

Timer B is an 8-bit up-counter which is incremented each time a clock pulse is input. The

two operation modes, interval and auto-reload, are explained below.

•

Interval timer operation

When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit

interval timer.

Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval

timing resume immediately after the reset. The clock input to timer B is selected from seven

internal clock signals output by prescaler S, or an external clock input at pin P10/IRQ0. The

selection is made by bits TMB2 to TMB0 of TMB.

After the count value in TCB reaches H'FF, the next clock signal input causes timer B to

overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in

interrupt enable register 2 (IENR2), a CPU interrupt is requested.*

At overflow, TCB returns to H'00 and starts counting up again.

During interval timer operation (TMB7 = 0), when a value is set in timer load register B

(TLB), the same value is set in TCB.

Note: * For details on interrupts, see 3.2.2, Interrupts.

Bit

Initial value

Read/Write

TLB7

TLB6

TLB5

TLB4

TLB3

TLB0

TLB2

TLB1

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