HD6433713 datasheet(189/324 Pages) RENESAS

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Bits 3 to 0: Clock select (SMR13 to SMR10)

Bits 3 to 0 select the clock supplied to SCI1.

Bit 3

Bit 2

Bit 1

Bit 0

Clock

Prescaler

SMR13 SMR12 SMR11

SMR10 Pin SCK1

Source

Divider Ratio

000

0SCK1 output Prescaler S

φ/1024

256

512

(initial value)

SCK1 output Prescaler S

φ/256

128

SCK1 output Prescaler S

φ/64

SCK1 output Prescaler S

φ/32

0SCK1 output Prescaler S

φ/16

SCK1 output Prescaler S

φ/8

SCK1 output Prescaler S

φ/4

SCK1 output Prescaler S

φ/2

—

Not used

—

··

1SCK1 input

External clock —

—

10.2.2 Serial Data Register U1 (SDRU1)

Note: * Not fixed

SDRU1 is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit

transfer (SDRL1 is used for the lower 8 bits).

Data written to SDRU1 is output to SDRL1 starting from the least significant bit (LSB), in

synchronization with the falling edge of the serial clock. This data is than replaced by LSB-first

data input at pin SI1, synchronized with the rising edge of the serial clock. In this way data is

shifted in the direction from the most significant bit (MSB) toward the LSB.

SDRU1 must be written or read only after data transmission or reception is complete.

If this register is read or written while a data transfer is in progress, the data contents are not

guaranteed.

The SDRU1 value upon reset is not fixed.

Serial Clock Period (µs)

φ = 4 MHz

φ = 2 MHz

Bit

Initial value

Read/Write

SDRU17

R/W

SDRU16

R/W

SDRU15

R/W

SDRU14

R/W

SDRU13

R/W

SDRU10

R/W

SDRU12

R/W

SDRU11

R/W

178

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