HD6433713 datasheet(198/324 Pages) RENESAS

198 / 324 page

Figure 10-3 SCI1 State Transitions

10.3.6 Serial Clock Error Detection

In the transfer state, if an extraneous pulse is superimposed on the normal serial clock signal due

to external noise, SCI1 may function incorrectly. Serial clock errors can be detected by means of

the procedure shown in figure 10-4.

In the transfer clock pending state, if more than the normal 8 or 16 serial clock cycles are

mistakenly input, SCI1 changes from the transfer state to the transfer clock pending state and then

back to the transfer state. After bit IRRS1 in interrupt request register 3 (IRR3) is cleared to 0,

writing a value in serial mode register 1 (SMR1) changes the state to serial start pending, and bit

IRRS1 is again set to 1.

Serial clock pending state

octal counter = 000 or

hexadecimal counter = 0000

Transfer state

octal counter / 000 or

hexadecimal counter / 0000

SMR1 write

(IRRS1

←

SMR1 dummy

read

(serial start)

8 or 16 serial

clock cycles

(internal clock)

(IRRS1

←

Serial clock

SMR1 dummy read (serial start)

(IRRS1

8 or 16 serial clock cycles

(external clock)

←

Serial start (SMR1 dummy read) pending state

octal counter = 000 or

hexadecimal counter = 0000

serial clock disabled.

187

HD6433713 Datasheet(PDF) 198 Page - Renesas Technology Corp