HD6433713 datasheet(196/324 Pages) RENESAS

196 / 324 page

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After data reception is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1.

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Read the received data from SDRL1 and SDRU1, as follows.

8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

When an internal clock source is used, a dummy read of SMR1 immediately starts a data receive

operation. The serial clock is output from pin SCK1.

When an external clock source is used, after the dummy read of SMR1, data is received in

synchronization with the serial clock input at pin SCK1. After data reception is complete, if the

serial clock continues to be input, reception resumes.

Executing a dummy read of SMR1 during reception will cause a receive error, setting bit IRRS1 in

IRR3 to 1.

Simultaneous transmit/receive

A simultaneous transmit/receive operation is carried out as follows.

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Set bits SO1, SI1, and SCK1 in PMR2 to 1, designating the SO1 output pin, SI1 pin, and

SCK1 pin functions. If necessary, set the SO1PMOS bit in PMR3 for NMOS open-drain

output at pin SO1.

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Set bit SMR16 in SMR1 to 1 or 0, and set bits SMR15 and SMR14 to a value other than 00,

designating 8- or 16-bit transfer mode. Select the serial clock with bits SMR13 to SMR10.

Writing data to SMR1 initializes the internal state of SCI1.

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Write transmit data in SDRL1 and SDRU1, as follows.

8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

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Execute a dummy read of SMR1. SCI1 starts operating: transmit data is output at pin SO1,

and receive data is input at pin SI1.

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After data transmission and reception are complete, bit IRRS1 in IRR3 is set to 1.

•

Read the received data from SDRL1 and SDRU1.

8-bit transfer mode:

SDRL1

16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1

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HD6433713 Datasheet(PDF) 196 Page - Renesas Technology Corp