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DP8344 Datasheet(PDF) 113 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 113 Page - National Semiconductor (TI) |
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113 / 184 page  50 Device Specifications (Continued) TABLE 5-16 Latched Read of IMEM (Note 1) Symbol ID Parameter Formula Min Max Units tSU-RRR-CO 1 RAE REM-RD Falling before CLK-OUT Rising 22 ns tH-RRR-X 2 RAE REM-RD Rising after XACK Rising 0 ns tSU-CMD-RRR 3 CMD Valid before RAE REM-RD Falling 0 ns tH-CMD-RRR 4 CMD Invalid after RAE REM-RD Falling Ta 26 ns tPD-RRR-X 5 RAE REM-RD Falling to XACK Falling 26 ns tPD-Xf-LCLr 6 XACK Falling to LCL Rising Tab5ns tPD-LCL-X 7 LCL Rising to XACK Rising (nIWa2)Tab10 8 ns tPD-Xr-LCLf 8 XACK Rising to LCL Falling Tab11 11 ns tAZ-A-LCL 9 A Disabled before LCL Rising TLab18 ns tZA-LCL-A 10 A Enabled after LCL Falling THab12 ns tPD-LCL-IMEM 11 LCL Rising to AD (IMEM) Valid Ta 22 ns tPD-IMEM-X 12 AD (IMEM) Valid to XACK Rising (nIWa1)Tab23 ns tPD-X-IMEM 13 XACK Rising to AD (IMEM) Invalid THa 1ns tPD-LCL-IA 14 LCL Falling to Next IA Valid (Note 2) TaTHab19 5 ns tW-IMEM 15 IMEM Valid (nIWa1)TaTHab9ns Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing specification may lead to invalid results Note 2 Two remote reads from instruction memory are necessary to read a 16-bit instruction word from IMEMlow byte followed by high byte The timing for the two reads are the same except that IA is incremented after the high instruction memory byte is read TLF9336 – 70 FIGURE 5-16 Latched Read of IMEM 113 |
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