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DP8344 Datasheet(PDF) 116 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 116 Page - National Semiconductor (TI) |
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116 / 184 page  50 Device Specifications (Continued) TABLE 5-19 Slow Buffered Write of IMEM (Notes 1 2) Symbol ID Parameter Formula Min Max Units tSU-RRW-CO 1 RAE REM-WR Falling before CLK-OUT Rising 24 ns tH-RRW-X 2 RAE REM-WR Rising after XACK Rising (Note 3) 0 ns Tab34 ns tSU-CMD-RRW 3 CMD Valid before RAE REM-WR Falling 0 ns tH-CMD-RRW 4 CMD Invalid after RAE REM-WR Falling Ta 26 ns tPD-RRW-X 5 RAE REM-WR Falling to XACK Falling 26 ns tPD-X-LCL 6 XACK Falling to LCL Rising Tab5ns tPD-LCL-X 7 LCL Rising to XACK Rising (nIWa2)Tab10 8 ns tPD-RRW-LCL 8 RAE REM-WR to LCL Falling Ta 5ns tAZ-AAD-LCL 9 A AD Disabled before LCL Rising TLab20 ns tZA-LCL-AAD 10 A AD Enabled after LCL Falling THab10 ns tPD-RDAT-I 11 AD (Data) Valid to I Valid 30 ns tH-RDAT-RRW 12 AD (Data) Invalid after RAE REM-WR Rising 14 ns tPD-LCL-IA 13 LCL Falling to next IA Valid TaTHab20 3 ns tPD-LCL-IWR 14 LCL Rising to IWR Falling b 3ns tPD-IWR-X 15 IWR Falling before XACK Rising (nIWa2)Tab19 ns tPD-RRW-IWR 16 RAE REM-WR Rising to IWR Rising 5 ns tZA-IWR-I 17 IWR Falling to I Enabled Tab2ns tAZ-IWR-I 18 IWR Rising to I Disabled 22 52 ns tPD-I-IWR 19 I Valid before IWR Rising (nIWa1)Tab10 ns tW-IWR 20 IWR Low (nIWa2)Tab2ns tPD-I-IA 21 I Disabled to IA Invalid 2TaTHab64 ns Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing specification may lead to invalid results Note 2 Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEMlow byte followed by high byte The timing for the 2nd write is shown in the following diagram The timing of the first write is the same as a write of the PC or RIC Note 3 The maximum value for this parameter is the latest RAE REM-WR can be removed without adding a T-state to the remote access 116 |
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