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DP8344 Datasheet(PDF) 138 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 138 Page - National Semiconductor (TI) |
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138 / 184 page  60 Reference Section (Continued) ANDA And with Accumulator Syntax ANDA Rs Rd register register ANDA Rs mIr register indexed Affected Flags N Z Description Logically ANDs the source register Rs to the active accumu- lator and places the result into the destination specified The destination may be either a register Rd or data memo- ry via an index register mode mIr Note that register bank selection determines which accumulator is active Example This example demonstrates a way to quickly unload all 11 bits of the three words in the Receiver FIFO when the FIFO is full The example assumes that the index register IZ points to the location in data memory where the information should be stored EXX 11 select alternate banks MOVE 00000111B A place the TSR mask into the accumulator Pop the first word from the receiver FIFO ANDA TSR IZa read bits 8 9 10 MOVE RTR IZa pop bits 0 – 7 Pop the second word from the receiver FIFO ANDA TSR IZa MOVE RTR IZa Pop the third word from the receiver FIFO ANDA TSR IZa MOVE RTR IZa Instruction Format ANDA Rs Rd 111100 Opcode Rd Rs 15 9 4 0 ANDA Rs mIr TLF9336 – 7 T-states ANDA Rs Rd 2 ANDA Rs mIr 3 Bus Timing ANDA Rs Rd Figure 6-1 ANDA Rs mIr Figure 6-7 Operation ANDA Rs Rd Rs AND accumulator xRd ANDA Rs mIr Rs AND accumulator xdata memory BIT Bit Test Syntax BIT rs n limited register immediate Affected Flags N Z Description Performs a bit level test by logically ANDing the source reg- ister rs to the immediate value n The affected flags are updated but the result is not saved Note that only the ac- tive registers R0 – R15 may be specified for rs The value n is 8 bits wide Example Poll the Transmitter FIFO Empty flag TFE in the Network Command Flag register NCF R1 waiting for the Trans- mitter to send the current FIFO data EXX 01 select main A alt B Poll BIT NCF10000000B All data sent yet JZ Poll No poll TFE Yes send next byte(s) Instruction Format 0111 Opcode n rs 15 11 3 0 T-states 2 Bus Timing Figure 6-1 Operation rs AND n 138 |
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