DP8344 datasheet(140/184 Pages) NSC

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60 Reference Section (Continued)

CPL

Complement

Syntax

CPL

Rsd

Affected Flags

N Z

Description

Logically complements the contents of the register Rsd

placing the result back into that register

Example

Load the fill-bit count passed from the host into the Trans-

mitter’s Fill-Bit Register

FBR

R3 and then perform the

required one’s complement of the fill-bit count In this exam-

ple register 20 contains the fill-bit count

EXX

select alternate banks

MOVE

R20 FBR

load FBR

CPL

FBR

complement fill-bit count

Instruction Format

10101110000

Opcode

Rsd

T-states

Bus Timing

Figure 6-1

Operation

Rsd

xRsd

EXX

Exchange Register Banks

Syntax

EXX

ba bb

Affected Flags

None

Description

Selects which CPU register banks are active by exchanging

between the main and alternate register sets for each bank

Bank A controls R0 – R3 and Bank B controls R4 – R11 The

table below shows the four possible register bank configura-

tions Note that deactivated registers retain their current val-

ues The Global Interrupt Enable bit GIE can be set or

cleared if desired

Active Register Banks

Main A Main B

Main A Alternate B

Alternate A Main B

Alternate A Alternate B

Example

Activate the main register set of Bank A the alternate regis-

ter set of Bank B and leave the Global Interrupt Enable bit

GIE unchanged

EXX

select main A alt B reg banks

Instruction Format

101011101

000

Opcode

00GIE not affected

01reserved

10Set GIE

11Clear GIE

T-states

Bus Timing

Figure 6-1

Operation

Case ba of

activate main Bank A

activate alternate Bank A

End case

Case bb of

activate main Bank B

activate alternate Bank B

End case

Case g of

leave GIE unaffected (default)

(reserved)

set GIE

clear GIE

End case

140

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