SEC1210 datasheet(32/218 Pages) MICROCHIP

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SEC1110/SEC1210

DS00001561C-page 32

 2013 - 2016 Microchip Technology Inc.

9.1.10

TIMER/COUNTER CONTROL REGISTER – TCON

The TCON Register reflects the current status of R8051XC2 Timer 0 and Timer 1 and it is used to control operation of

these modules. The tf0, tf1 (Timer 0 and Timer 1 overflow flags), ie0 and ie1 (External Interrupt 0 and 1 flags) will be

automatically cleared by hardware when the corresponding service routine is called.

TABLE 9-13:

TIMER/COUNTER CONTROL REGISTER

TCON

(SFR 0X88 - RESET=0X00)

TIMER/COUNTER CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

tf1

R/W

Timer 1 Overflow Flag:

Set by hardware when Timer 1 overflows. This flag can be cleared by

software and is automatically cleared when an interrupt is processed.

tr1

R/W

Timer 1 Run Control:

If cleared, Timer 1 stops.

tf0

R/W

Timer 0 Overflow Flag:

Set by hardware when Timer 0 overflows. This flag can be cleared by

software and is automatically cleared when an interrupt is processed.

tr0

R/W

Timer 0 Run Control:

If cleared, Timer 0 stops.

ie1

R/W

External Interrupt 1 Flag:

Set by hardware when an external interrupt int1 (edge/level,

depending on settings) is observed. It is cleared by hardware when

an interrupt is processed.

it1

R/W

External Interrupt 1 Type Control:

If set, External Interrupt 1 is activated at falling edge on input pin. If

cleared, External Interrupt 1 is activated at low level on input pin.

ie0

R/W

External Interrupt 0 Flag:

Set by hardware when an external interrupt int0 (edge/level,

depending on settings) is observed. Cleared by hardware when

interrupt is processed.

it0

R/W

External Interrupt 0 Type Control:

If set, External Interrupt 0 is activated at falling edge on input pin. If

cleared, External Interrupt 0 is activated at low level on input pin.

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