SEC1210 datasheet(85/218 Pages) MICROCHIP

85 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 85

SEC1110/SEC1210

10.14.1.2

Protocol Mode Register

The Guard Time reload registers EGT and BGT must be initialized to their desired values before writing to this register.

Changing them afterward may fail to register the change.

All non-reserved bits are read/write. The ATR bit may be set to 1 only if the TE1 bit is also set to 0. Valid settings for these

two bits are:

• ATR Mode: ATR=1 and TE1=0. In this Mode, the Protocol Timers and the Receiver are conditioned to expect an

ATR message from the ICC. Character framing is as per the T=0 protocol. This is the one case where the

Receiver does not wait for the SEC1110 and SEC1210 to transmit first; instead, it waits for a rising edge on the

SCx_RST_N pin, which is being controlled by the Guard Timer.

TABLE 10-38: SMART CARD GUARD ALGORITHM SPACING REGISTER

SC_GSR_LSB

(0X001B- RESET=0X00)

SMART CARD GUARD ALGORITHM SPACING REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

GUARD_ETUS_LSB

R/W

This register holds the LSB of maximum spacing between characters,

specified as the number of etus from the leading edges of consecutive

start bits.

TABLE 10-39: SMART CARD GUARD TIMER RELOAD A REGISTER

SC_EGT

(0X001C- RESET=0X00)

SMART CARD GUARD TIME RELOAD A REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

RELOAD_A

R/W

This register holds the Extra Guard Time value in T=0 or T=1 Mode.

In ATR Mode, this register holds the maximum number of etus

allowed from the rising edge of SCx_RST_N to the start bit of the TS

byte. If the timer elapses, the TSW Interrupt is asserted, and the

Receiver is disabled to the FIFO.

Values are expressed in units of etu.

The SC_PRM Register must be written after writing to this register, in

order to latch the change.

TABLE 10-40: SMART CARD GUARD TIMER RELOAD B REGISTER

SC_BGT

(0X001D- RESET=0X00)

SMART CARD GUARD TIME RELOAD B REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

RELOAD_B

R/W

This register holds the BGT value in T=1 Mode, or the DGT value in

T=0 Mode, preventing transmission until the specified number of etus

has elapsed since the last received character. Monitoring of

characters for this purpose does not depend on whether the Receiver

is enabled to the FIFO. This timer must be enabled, or it will not delay

transmission.

In ATR Mode, this register holds the desired width of the SCx_RST_N

pulse (Warm Reset) or the duration of the clock before the removal of

SCx_RST_N.

Values are expressed in units of etu.

The SC_PRM Register must be written after writing to this register, in

order to latch the change.

SEC1210 Datasheet(PDF) 85 Page - Microchip Technology

SEC1210 Datasheet(HTML) 85 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL