SEC1210 datasheet(91/218 Pages) MICROCHIP

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 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 91

SEC1110/SEC1210

TABLE 10-54: SMART CARD TEST REGISTER

SC_TEST3

(0X0032 - RESET=0XFF)

SMART CARD TEST REGISTERS

BIT

NAME

R/W

DESCRIPTION

7:0

TEST3[7:0]

R/W

This field defines the number of SC block clock time between the

events

• Reset assertion and clock stop during hardware auto-deactivation

• Clock stop and SCx_VCC switch off signal to smart card pins

TABLE 10-55: SMART CARD TEST REGISTER

SC_TEST4

(0X0033~0033, - RESET=0X00)

SMART CARD TEST REGISTERS

BIT

NAME

R/W

DESCRIPTION

7:0

START_WIDTH_TOL[15:8]

R/W

The start width tolerance is a 16-bit wide register. Bits 1:0 are used

for OEN_EXT, START_BIT_NEG_EDGE also.

TABLE 10-56: SMART CARD TEST DEBOUNCE REGISTER

SC_TEST0

(0X0035, - RESET=0X00)

SMART CARD TEST REGISTERS

BIT

NAME

R/W

DESCRIPTION

7:4

Reserved

Always read as 0

3:1

OEN_CLKS

R/W

These 3 bits of FAST_DEBOUNCE[2:0] are reused as OEN_CLKS field.

It indicates the number of internal Smart Card block clocks to extend

OEN for SCx_IO pad. This field is used when OEN_EXT bit is set.

000

: 2 clocks

001

: 2 ~ 4 clocks in SEC1110/SEC1210. 4 clocks in later versions

010

: 4 ~ 8 clocks in SEC1110/SEC1210. 8 clocks in later versions

011

: 8 ~ 16 clocks in SEC1110/SEC1210. 16 clocks in later versions

100

: 16~ 32 clocks in SEC1110/SEC1210. 32 clocks in later versions

101

: 32 ~ 64 clocks in SEC1110/SEC1210. 64 clocks in later versions

Reserved

R/W

Must be 0.

TABLE 10-57: SMART CARD FIFO TEST REGISTER

SC_FIFO_TEST

(0X0100~02FF, - RESET=0XXX)

SMART CARD FIFO TEST1

BIT

NAME

R/W

DESCRIPTION

7:0

FIFO_TEST

R/W

The SC_FIFO is memory mapped to the 8051 CPU on the XDATA

bus. Only the first 261 (259 for SEC1110/SEC1210) bytes are valid,

and rest is an alias access.

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