SEC1210 datasheet(64/218 Pages) MICROCHIP

64 / 218 page

SEC1110/SEC1210

DS00001561C-page 64

 2013 - 2016 Microchip Technology Inc.

The Guard Spacing Register (GSR) is programmed by software with the expected maximum spacing between received

characters in units of etus, including Extra Guard Time EGT. (This is required in a separate register by the implemen-

tation). The value in the GSR is interpreted as a maximum amount of time allowed from start bit to start bit, and so it

must be at least 12 etus.

As each new character is received within this window, an internal counter (CPT) is decremented once. This counter

restarts, starting from the maximum legal number of characters in a packet (258 for T=0, 259 for T=1) as soon as char-

acters start being received in an exchange, regardless of whether the Receiver remains enabled or not, and regardless

of errors. The CPT counter reloads and stops when no character is received within the GSR window.

If software attempts to transmit while this counter is still active, the transmission is inhibited and held pending. If, how-

ever, while a transmission is pending, the CPT count underflows, then the transmission is abandoned, and the TF error

(Transmit Failure) is posted, which is an interrupt. See Figure 10-12 for this case. Note that, in T=0 Mode, the Incoming

or Outgoing filter remains applied as selected, so that any procedure bytes (NUL, INS, and INS) are not counted.

If there is no such error, then, after the vacant window time has passed, the Transmitter waits for the Designated Guard

Time amount (DGT or BGT) and begins transmitting. See FIGURE 10-13: Guard Time Algorithm, No Error, Transmit

Held on page 65 for this case.

FIGURE 10-12:

GUARD TIME ALGORITHM WITH ERROR, TRANSMIT ABANDONED

. . .

Last

Expected

1st

Unexpected

2nd

Unexpected

Last Legal

1st Illegal

FRE

FTE

LSR bit 5

Error: Transmit attempted and Card has been transmitting too long.

All durations within limit

Interrupt

posted

SCx_IO

Count Violated

Limit = GSR register at offset 0x001B

SW attempts new

exchange, Transmitter waits

SW reads

LSR

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