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SEC1210 Datasheet(PDF) 4 Page - Microchip Technology

Part # SEC1210
Description  Smart Card Bridge to USB and UART Interfaces
PDF  218 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SEC1210 Datasheet(HTML) 4 Page - Microchip Technology

  SEC1210 Datasheet HTML 1Page - Microchip Technology SEC1210 Datasheet HTML 2Page - Microchip Technology SEC1210 Datasheet HTML 3Page - Microchip Technology SEC1210 Datasheet HTML 4Page - Microchip Technology SEC1210 Datasheet HTML 5Page - Microchip Technology SEC1210 Datasheet HTML 6Page - Microchip Technology SEC1210 Datasheet HTML 7Page - Microchip Technology SEC1210 Datasheet HTML 8Page - Microchip Technology SEC1210 Datasheet HTML 9Page - Microchip Technology Next Button
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SEC1110/SEC1210
DS00001561C-page 4
 2013 - 2016 Microchip Technology Inc.
1.0
INTRODUCTION
The SEC1110 and SEC1210 provide a single-chip solution for a Smart Card bridge to USB and UART interfaces. These
bridges are controlled by an enhanced 8051 micro controller and all chip peripherals are accessed and controlled
through the SFR or XDATA register space.
1.1
Features
• Smart Card
- Fully compliant with standards: ISO/IEC 7816, EMV 4.2/4.3, ETSI TS 102 221 and PC/SC
- Versatile ETU rate generation, supporting current and proposed rates (to 826 Kbps and beyond)
- Full support of both T=0 and T=1 protocols
- Full-packet FIFO (261 bytes), for transmit and receive
- Half-duplex operation, with no software intervention required between Transmit and Receive phases of an
exchange
- Very loose real-time response required of software: approximately 180 ms worst case
- Dynamically programmable FIFO threshold, with byte granularity
- Time-out FIFO flush interrupt, independent of threshold
- Programmable Smart Card clock frequency
- UART-like register file structure
- Supports Class A, Class B, Class C, or Class AB Smart Cards (all 1.8 V, 3.0 V and 5.0 V cards)
- Automatic character repetition for T=0 protocol parity error recovery
- Automatic card deactivation on card removal and on other system events, including persistent parity errors
- Internal procedure byte filtering for T=0 protocol
- Protocol timers (guard, time-out and CWT) for EMV-defined timing parameters
- Detection of an unresponsive card
- Activation/deactivation sequences
- Cold/warm resets
- Monitoring for all EMV timing constraints
- 16-bit general purpose down counter for software timing use
- Fully compliant ESD protection on card pins per JESD22-A114D (March 2006) and JESD22-A115A “Machine
Model” from AN1181
- Fully EMV compliant, internal signal current limits
- 3.3 V internal operation with 5.0 V tolerant buffers where required
- Self-contained management of Smart Card power:
- SC1_VCC and SC2_VCC, supply output
- Regulator for 1.8 V, 3.0 V, and 5.0 V from supply input
- Current limiter with over-current sense interrupt (short circuit detect)
- Hardware-ensured, compliant deactivation sequence on card removal
- Synchronous card support
•USB
- 12 Mbps USB operation compliant with the USB 2.0 Specification
- Integrated USB 1.5 K pull-up resistor
- Integrated Series resistors on USB_DP, USB_DM
- Integrated USB devices controller with:
- 8/16/32/64 byte control endpoint 0 buffer
- Five 8/16/32/64 byte programmable (bulk/interrupt) endpoint buffers
• 8051
- Reduced instruction cycle time (approximately 9 times 80C51)
- 9.6 MHz max clock speed
- Enhanced peripherals: two 16-bit timers, watch dog timer, interrupt controller, JTAG
- 16 KB One Time Programmable (OTP) ROM
- 1.5 KB RAM
- 4 KB (SEC1100/SEC1200)/ 16KB (SEC1110/SEC1210) ROM



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