SEC1210 datasheet(69/218 Pages) MICROCHIP

69 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 69

SEC1110/SEC1210

The pads SCx_RST_N, SCx_CLK, SCx_IO, SCx_C4, SCx_C8 are controlled by the SCC block when GPIO[4:0] for

Smart Card1 and GPIO[18:16] for Smart Card2 are in GPIO Auxiliary A Mode. The GPIO5 must also be in Auxiliary A

Mode to support LED functionality for both Smart Cards.

The INF_IDLE_IO_EN, INF_IDLE_IO_VAL bits may be used during Smart card activation and deactivation sequence

to ensure SCx_RST_N, SCx_CLK, SCx_IO, SCx_C4, SCx_C8 pins are low even in the presence of external pull-up

loads.

10.11.1

AUTOMATIC CONTROL OF IDLE CONDITION ON SMART CARD INTERFACE

Smart Card specification requires that the interface signals be held at zero until a card is inserted, power is applied to

the card, and the reset sequence is started. The INF_IDLE_CTL_EN bit works in conjunction with the INTERFACE_EN-

ABLE

bit to do this. When the interface is in the idle state, (INTERFACE_ENABLE=0), pull-downs are enabled, and the

control signals are driven zero. As soon as the interface is enabled, (INTERFACE_ENABLE=1) control of IO pad signals

reverts to the Smart Card Controller (SCC). See figure FIGURE 10-14: on page 66.

The INF_IDLE_CTL_EN bit asserts the pull-down (67 K

) to the Smart Card pads, which may be insufficient to ensure

VOL is met in the presence of external pull-up loads. Hence the GPIO mode must be used during the activation and

deactivation sequence.

10.12 Synchronous Interface Registers

All registers in the Synchronous Interface are byte addressable. This allows the firmware to toggle the output using byte

writes without affecting any other register bits. There are five control lines associated with the interface that are con-

trolled by five identical registers.

Each of the Synchronous Interface registers consists of two bytes, a low address byte and a high address byte.

Note:

In SEC1110/SEC1210 version of the chip, the INF_IDLE_CTL_EN bit asserts the pull-down (67 k

) to the

Smart Card pads, which may be insufficient to ensure Vol is met in the presence of external pull-up loads.

Hence the GPIO mode must be used during the activation and deactivation sequence.

TABLE 10-6:

SMART CARD CURRENT CONTROL REGISTER

PAD_CTL_SC

(0X0081 - RESET=0X00)

PAD CURRENT CONTROL

BIT

NAME

R/W

DESCRIPTION

7:2

Reserved

Always read as 0

1:0

SEL

R/W

This register is not used.

TABLE 10-7:

SMART CARD SYNC RST CONTROL REGISTER

SC_SYNC_RST

(0X0091- RESET=0X00)

SMART CARD CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

7:6

Reserved

Always read as 0

5INPUT_EN

R/W

: Input is enabled

: Input is disabled

OUTPUT_EN

R/W

: Output is enabled

: Output is disabled

FAST_OPEN_DRAIN

R/W

If this bit is set, and the Mode is Output, the signal is driven low when

the data is 0. When the data transitions to 1, it is actively driven high

for one clock cycle before being tri-stated.

OPEN_DRAIN

R/W

If this bit is set, and the Mode is Output, the SCx_RST_N output is

driven open drain; 0 are driven, 1 are tri-stated.

PULL_UP_EN

R/W

When set, it enables the pull-up to this pin.

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