SEC1210 datasheet(43/218 Pages) MICROCHIP

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DS00001561C-page 43

SEC1110/SEC1210

The SPSTA Register contains flags to signal data transfer complete, write collision, and inconsistent logic level on

SPI1_CE (Slave select) pin (mode fault error).

9.1.25

SPI1 SERIAL PERIPHERAL CONTROL REGISTER – SPCON

The Serial Peripheral Control Register is used to configure the SPI module. It selects the Master clock rate, selects the

serial clock polarity and phase, enables the SPI1_CE input, and enables/disables the whole SPI1 module.

modf

Mode Fault Flag:

Set by hardware when the SPI1_CE pin level is in conflict with the

actual mode of the SPI_MS controller (configured as Master while

externally selected as Slave).

Cleared by hardware when the ssn pin is at appropriate level. Can be

also cleared by software by reading the SPSTA Register with modf

set.

3:0

Reserved

Always read as 0

TABLE 9-35:

SPI1 SERIAL PERIPHERAL CONTROL REGISTER

SPCON

(SFR 0XE2 - RESET=0X14)

SERIAL PERIPHERAL (SPI1) CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

spr2

R/W

Serial Peripheral Rate 2:

Together with spr[1:0] defines the clock rate in Master Mode.

spen

R/W

Serial Peripheral Enable:

When cleared, disables the SPI1 Interface. When set enables the

SPI1 Interface.

ssdis

R/W

SS Disable:

When cleared enables the SPI1_CE input. When set disables the

SPI1_CE input.

When ssdis is set, no SPSTA.modf interrupt request will be generated.

mstr

R/W

Serial Peripheral Master:

When set configures the SPI1 as a Master.

cpol

R/W

Clock Polarity:

When cleared, the SPI1_CLK is set to 0 in idle state. When set, the

SPI1_CLK is set to 1 in idle state.

cpha

R/W

Clock Phase:

When cleared, data is sampled when the SPI1_CLK leaves the idle

state (see SPCON.cpol). When set, data is sampled when the

SPI1_CLK returns to idle state (see SPCON.cpol).

1:0

spr[1:0]

R/W

Serial Peripheral Rate:

Together with spr2 specify the serial clock rate in Master Mode.

TABLE 9-34:

SPI1 SERIAL PERIPHERAL STATUS REGISTER

SPSTA

(SFR 0XE1 - RESET=0X00)

SERIAL PERIPHERAL (SPI1) STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

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