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SEC1210 Datasheet(PDF) 20 Page - Microchip Technology |
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SEC1210 Datasheet(HTML) 20 Page - Microchip Technology |
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20 / 218 page ![]() SEC1110/SEC1210 DS00001561C-page 20 2013 - 2016 Microchip Technology Inc. . 7.1 Sleep/Power Management The R8051XC2 has a power management control unit that generates clock enable signals for the main CPU and for peripherals; serves Power Down Modes IDLE and STOP; and generates an internal synchronous reset signal (upon external reset, watchdog timer overflow, or software reset condition). The IDLE Mode leaves the clock of the internal peripherals running. Any interrupt will wake the CPU. The STOP Mode turns off all internal clocks. The CPU will exit this state when an external interrupt (0 or 1)or reset occurs and internally generated interrupts are disabled since they require clock activity. The Wake-up From Power-Down Mode control unit services two external interrupts during power-down modes. They can combinationally force the clock enable outputs back to active state so the clock generation can be resumed. FIGURE 7-1: R8051XC2 Block Diagram R8051XC2 CPU 256 Bytes IRAM SFR Registers OCDS EASE on-chip Debugging block and JTAG Interface Timer 0 Timer 1 Watchdog Timer External Interrupts Power Management, Reset & Wake-Up Control Units SFR Mux CLK_PWR SmartCard1, 2* ISR 8051-compatible External Memory ref_clk SPI1 UART JTAG SC1, SC2 SMSC Trace FIFO, SPI XIP SPI2 XDATA SRAM Oscillators Clkper Peripherals GPIO GPIO USB ROM Timer 2 SPI Master 16550 UART UDC OTP ROM * SEC1210 only |
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