SEC1210 datasheet(74/218 Pages) MICROCHIP

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SEC1110/SEC1210

DS00001561C-page 74

 2013 - 2016 Microchip Technology Inc.

10.13 Power

The Smart Card block is enabled when the SC1_CLK_EN (or SC2_CLKEN) is turned on in the SC1_CLK_DIV (or SC2_-

CLK_DIV) Register.

10.14 Asynchronous Interface Registers

The SEC1110 and SEC1210 have Smart Card Interfaces based on the ISO/IEC 7816 Standard.

10.14.1

ASYNCHRONOUS MODE REGISTERS

TABLE 10-13: SMART CARD TRANSMIT/RECEIVE BUFFER REGISTER

SC_TBR_RBR

(0X0000- RESET=0XXX)

SMART CARD TRANSMIT/RECEIVE BUFFER REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

DATA

R/W

Writing to this register causes the byte to be written to the FIFO, and

an internal count is incremented for determining the length of the

message to be transmitted. Writing too much information will cause

the message to be silently truncated to the length of the FIFO.

Reading from this register causes a byte to be read from the FIFO.

This decrements the FIFO Count Register. If the FIFO Count Register

is already zero, this causes the UE bit in the Line Status Register to

be set to 1, and the Receiver is disabled from writing to the FIFO.

TABLE 10-14: SMART CARD INTERRUPT ENABLE REGISTER

SC_IEN

(0X0001- RESET=0X00)

SMART CARD INTERRUPT ENABLE REGISTER

BIT

NAME

R/W

DESCRIPTION

7PRTI

R/W

: Enables the Protocol and Timer Interrupt. The sources of this

interrupt are itemized in register PRIP.

AUTO_DA_PWR_OFF

R/W

For the SEC1110 and SEC1210 A0 version, this bit is not used.

In the SEC1110 and SEC1210 A1 version onwards, the behavior is as

follows:

When this bit is set to 1, it indicates that SCx_VCC power is turned

off automatically during auto-deactivation. Auto-deactivation occurs

when a Smart Card is removed (SCx_PRSNT_N goes high), or the

APDE

bit is set and a non-recoverable parity error is encountered.

This bit must not be set to 1 in SEC1110 and SEC1210 A1 version,

for Class A, Class B modes.

When this bit is set to 0 (default), it indicates that the hardware will

go through the auto-deactivation sequence of driving RST, CLK, and

IO lines low, but not power down SCx_VCC. An interrupt is raised

when auto-deactivation occurs and software must follow the power

down sequence. The interrupt source is from the GPIO (Card remove)

due to the RLSI (non-recoverable parity error).

GPI

R/W

Set to 0. Do not use for SEC1110 and SEC1210.

PTI

R/W

Set to 0. Do not use for SEC1110 and SEC1210.

Reserved

R/W

Always write 0

2RLSI

R/W

: Enables an interrupt on Line Status errors: Parity, Framing,

Overflow or Underflow.

THRRI

R/W

: Enables an interrupt when the Transmitter has finished

transmission of a message, including the minimum Guard Time (stop

bits).

0RDAI

R/W

: Enables an interrupt when FIFO data is available to read, either

by the threshold value or by any data at all in the FIFO after a timeout

condition (e.g., the CWT Timer).

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