SEC1210 datasheet(89/218 Pages) MICROCHIP

89 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 89

SEC1110/SEC1210

10.14.1.4

FIFO Count Registers

This register pair holds the number of bytes currently in the FIFO.

While setting up for transmission, and during transmission, this register tracks bytes being transmitted. If there is an

error in transmission, the Transmitter stops and this register holds the number of bytes remaining in the FIFO. In case

of a transmission error, the FIFO must be reset using the FRST bit in the FCR Register. This action will also clear these

registers to zero. During transmission (i.e., while the Receiver is not active), the value in these registers is not compared

against the Threshold value in the FTHL/FTHM register pair.

While the Receiver is active, this register pair also tracks the number of bytes in the FIFO, and this value is compared

against the FIFO Threshold in the FTHL/FTHM register pair in order to provide the FIFO Threshold Interrupt.

To determine whether an error happened during the Transmit or Receive phase of an exchange (and hence which count

is being displayed in this register), software may inspect the ETR bit in the Line Status Register.

TABLE 10-47: SMART CARD FIFO THRESHOLD MSB REGISTER

SC_FTHM

(0X0029- RESET=0X00)

SMART CARD FIFO THRESHOLD MSB REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

FIFO_THRESHOLD_HI

R/W

This register hold the MSB FIFO threshold for received bytes.

TABLE 10-48: SMART CARD FIFO COUNT LSB REGISTER

SC_FCL

(0X002A- RESET=0X00)

SMART CARD FIFO COUNT LSB REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

FIFO_COUNT_LO

R/W

This register holds the LSB of the FIFO count in bytes.

TABLE 10-49: SMART CARD FIFO COUNT MSB REGISTER

SC_FCM

(0X002B- RESET=0X00)

SMART CARD FIFO COUNT MSB REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

FIFO_COUNT_HI

R/W

This register holds the MSB of the FIFO count in bytes.

TABLE 10-50: SMART CARD FILTER LENGTH REGISTER

SC_FLL

(0X002C- RESET=0X00)

SMART CARD FILTER LENGTH REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

FILTER_LEN

R/W

This register holds the number of expected data bytes in a T=0

exchange, for the sake of the T=0 filter state machines.

This register is decremented as needed by the outgoing filter state

machine. An initial value of 00h, when the outgoing filter is activated,

is interpreted as 256. An initial value of 00h, when the incoming filter

is activated, is interpreted as 0. Any T=0 command that does not

involve a data transfer will use the incoming filter with an initial count

of 00h. This register returns the least-significant 8 bits of the current

count value when read.

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