SEC1210 datasheet(98/218 Pages) MICROCHIP

98 / 218 page

SEC1110/SEC1210

DS00001561C-page 98

 2013 - 2016 Microchip Technology Inc.

11.2

Control Transactions

11.2.1

SETUP STAGE

Receiving Setup packets is the same as receiving bulk out packets, except that the RXSETUP bit in the USB_EPn_CT-

L_REG Register is set by the USB controller instead of the RXOUTB bit to indicate that an Out packet with a Setup PID

has been received on the Control Endpoint. When the RXSETUP bit has been set, all the other bits of the USB_EPn_CT-

L_REG Register are cleared and an interrupt is triggered, if enabled. The firmware has to read the Setup request stored

in the Control Endpoint data before clearing the RXSETUP bit to free the endpoint data for the next transaction.

11.2.2

DATA STAGE: CONTROL ENDPOINT 0 DIRECTION

The data stage management is similar to bulk management.

A control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are

managed as half-duplex endpoint: IN or OUT.

There are separate Read and Write buffers for Control Endpoint 0.

• If the data stage consists of INs, the firmware writes the data buffer and sets to 1 the TXRDY (or BUF0_RDY) bit in

the USB_EPn_CTL_REG (or USB_EPn_BUFRDY_REG) Register. The IN transaction is complete when the

TXRDY

(or BUF0_RDY) bit has been reset by the hardware.

• If the data stage consists of OUTs, the RXOUTB (and BUF0_RDY) bit is set by hardware when a new valid packet

has been received on the endpoint. The firmware must read the data stored into the buffer and then clear the

RXOUTB

(or BUF0_RDY) bit to reset the buffer and to allow the next transaction.

To send a STALL handshake, see Section 11.4.

11.2.3

STATUS STAGE

The status stage management is similar to bulk management.

• For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length

Packet (see “Bulk/Interrupt IN Transactions In Standard Mode” on page). To send a STALL handshake, see

Section 11.4.

• For a Control Read transaction, the status stage consists of an OUT Zero Length Packet.

11.3

USB Reset

The USB_RESET_INT bit in the USB_INT_REG Register is set by hardware when a Reset has been detected on the USB

bus. This triggers a USB interrupt, if enabled. The USB controller is still enabled. The End of USB Reset can be deter-

mined by reading the USB_RESET_STS bit in UDC Status Register.

11.4

STALL Handshake

This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the

USB_EPn_CTL_REG Register to send a STALL handshake at the next request of the Host on the endpoint. The

RXSETUP

, TXRDY, RXOUTB bits must be first reset to 0. The bit UNSUCESSFUL is set to 1 by the USB controller when a

STALL has been sent. This triggers an interrupt if enabled.

The firmware should clear the STALLRQ and UNSUCESSFUL bits after each STALL sent. The STALLRQ bit is cleared

automatically by hardware when a valid SETUP PID is received on a Control type endpoint.

11.5

Start of Frame Detection

The USB_SOF_INT bit in the USB_INT_REG Register is set when the USB controller detects a Start of Frame PID. This

triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. The

SOF_MISSED

bit is set if within 16383 FS bits times, a SOF frame is not received. The SOF_GOOD bit is set if SOF frame

is received and the timestamp matches the expected value. After initialization or loss of frame sync, the timestamp value

is loaded when an SOF is received.

11.6

Data Toggle Bit

The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted by the USB controller and

cleared by hardware when a DATA 1 packet is received and accepted by the USB controller. This bit is reset when the

firmware resets the endpoint data buffer using the UEPRST Register.

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