SEC1210 datasheet(75/218 Pages) MICROCHIP

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DS00001561C-page 75

SEC1110/SEC1210

10.14.1.1

Interrupt Identification

By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority

interrupt exist with a descending order of priority as follows:

Receiver line status (highest priority)

Received data ready

Transmitter holding register empty or threshold has been reached

Protocol/Timer Interrupt

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the SC Interrupt

Identification Register (refer to interrupt control table). When the CPU accesses the IIR, the Smart Card Interface

freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the

Smart Card Interface records new interrupts, the current indication does not change until either the interrupt is re-

enabled or the event causing the interrupt is cleared and re-asserted. The contents of the SC_IIR are described below.

Note:

The traditional UART FIFO Control Register functions are no longer in a write-only register at this address.

Instead, the FCR Register is a read/write register at location offset 0x0012, and the Threshold is in a

separate pair of registers.

Note:

Interrupts are re-enabled by writing a 1 to the interrupt enable bit. This bit does not need to be cleared to

re-enable interrupts.

TABLE 10-15: SMART CARD INTERRUPT IDENTIFICATION REGISTER

SC_INT_ID

(0X0002- RESET=0B00XX00XX1)

SMART CARD INTERRUPT IDENTIFICATION REGISTER

BIT

NAME

R/W

DESCRIPTION

7PRTI

R/W

: Indicates the presence of a Protocol or Timer Interrupt. The

sources of this interrupt are itemized in register PRIP, and are cleared

by reading that register.

AUTO_DA_PWR_OFF

R/W

This bit is not used in the SEC1110/SEC1210 version.

In SEC1110/SEC1210 version onwards, the behavior is as follows:

This bit is set to 1 if the SC_IEN.AUTO_DA_PWR_OFF bit is set, and an

auto-deactivation event occurred.

This bit is cleared when both the SC_INTF_MON.CRMV bit and

SC_LCR.APDE

bits are cleared by software.

GPI

R/W

Do not use, SC_IEN to keep disabled

PTI

R/W

Do not use, SC_IEN to keep disabled

FTO

R/W

FIFO Timeout:

: Indicates a FIFO Data Timeout caused by the CWT Timer, or by

the Timeout Timer in T=0 Mode, rather than the amount of received

data reaching the Threshold value. It also indicates that the Receiver

will be delivering no more data bytes to the FIFO.

This bit is not an interrupt source, but is instead a status bit, which

should be examined when processing the RDAI Interrupt. This bit is

cleared by emptying or resetting the FIFO.

2:1

PRI

R/W

If the IP bit in this register is 0 (active), then this field holds the source

of the interrupt

0IP

R/W

: Indicates that an interrupt is pending, and that the PRI field of this

: Indicates that no interrupt is pending.

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