SEC1210 datasheet(79/218 Pages) MICROCHIP

79 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 79

SEC1110/SEC1210

TABLE 10-21: SMART CARD INTERFACE CONTROL REGISTER

SC_ICR

(0X0007- RESET=0B00001000)

SMART CARD INTERFACE CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

7RST_N

R/W

SCx_RST_N Pin Control:

The default value (0) holds the SC_RST_N pin low. A 1 in this bit

causes the SCx_RST_N pin to drive high. This bit may be written to 1

or 0 by software, and the first underflow of the Guard Timer, while the

Protocol Mode Register is indicating ATR Mode, sets this bit to 1, and

causes the SC_RST_N pin to rise as part of the Reset/ATR sequence.

ENG

R/W

Enable Guard Timer:

Writing 1 enables the Guard Timer to begin counting at the next

triggering event. Writing 0 has no effect: to clear this bit, write 1 to the

RSG

bit in the Timer Control Register. This bit is cleared by hardware

in ATR Mode when the first start bit is seen, or on an underflow from

the BGT reload. In the second case, an interrupt request is also

presented

5:4

VPIN

R/W

Not used.

CSTP

R/W

Clock Stop:

: Stops the SCx_CLK signal either high or low, depending on the

CSTL

bit.

: Causes the SCx_CLK signal to run. This signal is initially 1 on

reset, causing SCx_CLK to be stopped in the low state.

When setting this bit, the CPU clock must be multiple of SCx_CLK

and CPU frequency must not be changed. Otherwise a clock glitch

can occur on SCx_CLK. To avoid this, software synchronization must

be done to read SCx_CLK and CSTP bit must be set with CSTL=0

when SCx_CLK is low.

CSTL

R/W

Clock Stop Level:

When the CLKSTP bit is set, this bit indicates the state in which the

SCx_CLK pin should stop: 1 means stop the clock high, 0 means stop

the clock low. This bit is initially 0 on reset, causing SCx_CLK to be

stopped in the low state.

R/W

SCx_IO Pin Control:

The default value (0) forces the SCx_IO pin low. Writing a 1 to this bit

enables the SCx_IO pin to float and to drive high.

IOPU

R/W

1 : Enables a weak pull-up device on the SCx_IO pin. This device is

internally disabled while the Transmitter is actively driving the SCx_IO

pin.

TABLE 10-22: SMART CARD DATA REGISTER

SC_DATA

(0X0008~0X000B- RESET=0XXX)

SMART CARD DATA REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

DATA

R/W

Perform all transfers at the location DATA, regardless of size.

Transferring a value at the DATA location has the same effect as

transferring the individual bytes (LS byte first) at the SC_TBR_RBR

location (0000), but is more efficient for the larger data types.

In the SEC1110 and SEC1210, these registers are present for

software compatibility to other parts.

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