SEC1210 datasheet(34/218 Pages) MICROCHIP

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SEC1110/SEC1210

DS00001561C-page 34

 2013 - 2016 Microchip Technology Inc.

9.1.12

TIMER 0,1,2 – TH0, TL0, TH1, TL1, TH2, TL2

• TH0, TL0 registers reflect the state of Timer 0. TH0 holds higher byte and TL0 holds lower byte.

• Timer 0 can be configured to operate as either a timer or counter.

• TH1, TL1 registers reflect the state of Timer 1. TH1 holds the higher byte and TL1 holds the lower byte.

• Timer 1 can be configured to operate as either a timer or counter.

• TH2, TL2 registers reflect the state of Timer 2. TH2 holds the higher byte and TL2 holds the lower byte.

• Timer 2 can be configured to operate in compare, capture or reload modes.

9.1.13

TIMER 2 CONTROL REGISTER – T2CON

The T2CON Register reflects the current status of the R8051XC2 Timer 2 and is used to control Timer 2 operation.

TABLE 9-16:

TIMER 0, 1, AND 2 LOW BYTE

TL0

(SFR 0X8A - RESET=0X00)

TL1

(SFR 0X8B - RESET=0X00)

TL2

(SFR 0XCC - RESET=0X00)

TIMER 0/1/2 LOW BYTE

BIT

NAME

R/W

DESCRIPTION

7:0

TL0[7:0]/TL1[7:0]/ TL2[7:0]

R/W

Timer 0/ Timer 1/Timer 2 Low Byte

TABLE 9-17:

TIMER 0, 1, AND 2 HIGH BYTE

TH0

(SFR 0X8C - RESET=0X00)

TH1

(SFR 0X8D - RESET=0X00)

TH2

(SFR 0XCD - RESET=0X00)

TIMER 0/1/2 HIGH BYTE

BIT

NAME

R/W

DESCRIPTION

7:0

TH0[7:0]/ TH1[7:0]

R/W

TImer 0/ Timer 1/Timer 2 High Byte

TABLE 9-18:

TIMER 2 CONTROL REGISTER

T2CON

(SFR 0XC8 - RESET=0X00)

TIMER 2 CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

t2ps

R/W

Prescaler Select:

: Timer 2 is clocked with 1/12 of the oscillator frequency.

: Timer 2 is clocked with 1/24 of the oscillator frequency.

i3fr

R/W

Active edge selection for external interrupt “int3”, (used also as a

compare and capture signal):

: Falling edge

: Rising edge

i2fr

R/W

Active edge selection for external interrupt “int2”:

: Falling edge

: Rising edge

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