SEC1210 datasheet(83/218 Pages) MICROCHIP

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DS00001561C-page 83

SEC1110/SEC1210

Note 1: This register provides control for FIFO access, and enables the Receiver and the Transmitter.

2: In SEC1110/SEC1210 version, if the FIFO is disabled before a GSR timeout occurs, then the GSR timer is

not reset. The software work-around is to wait for the GSR timer to expire. This Anomaly 6 is fixed in later

versions (SEC1110/SEC1210).

RSE

R/W

Receiver Sampling Enable:

1 written to this bit enables the Receiver to sample the SCx_IO pin

for characters. In ATR Mode, the sampling does not occur

immediately, but waits for a rising edge on the SCx_RST_N pin first.

This bit is cleared by an incoming error (e.g., repeated parity error in

T=0 Mode, or CWT violation in T=1 Mode, or Overrun Error). While

the Receiver is sampling, the BGT or DGT value in the Guard Timer

the state of the FRE bit.

FRST

FIFO Reset:

Always reads as 0. A 1 written to this bit resets the FIFO to an Empty

state. If an error has occurred while transmitting to the card, this

function must be used to re-initialize the FIFO.

FRE

R/W

FIFO Receive Enable:

Allows reception into the FIFO. Except in ATR Mode, a transmission

has to occur before the Receiver is actually activated. In ATR Mode,

a rising edge must occur on the SCx_RST_N pin before the Receiver

is activated. This bit is turned off by errors occurring during reception

or transmission (e.g., CWT timeout error); otherwise software must

turn it off after receipt of a message, to prepare for the next exchange

FTE

R/W

FIFO Transmit Enable:

Writing 1 to this bit triggers transmission from the FIFO. This bit is

turned off by the normal end of transmission, when all bytes in the

FIFO have been transmitted. It is also turned off by errors occurring

during transmission (e.g., parity error after retransmissions in T=0

Mode).

TABLE 10-30: SMART CARD TIMEOUT TIMER LEAST SIGNIFICANT BYTE (LSB) RELOAD

SC_TOL

(0X0014- RESET=0X00)

SMART CARD TIMEOUT TIMER LSB RELOAD REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

TIMER_RELOAD_LO

R/W

This register holds the LSB of the reload value for the Timeout Timer.

TABLE 10-31: SMART CARD TIMEOUT TIMER MIDDLE SIGNIFICANT BYTE (MSB) RELOAD

SC_TOM

(0X0015- RESET=0X00)

SMART CARD TIMEOUT TIMER MIDDLE MSB RELOAD

BIT

NAME

R/W

DESCRIPTION

7:0

TIMER_RELOAD_MI

R/W

This register holds the middle MSB of the reload value for the Timeout

Timer.

TABLE 10-29: SMART CARD FIFO CONTROL REGISTER (CONTINUED)

SC_FCR

(0X0012- RESET=0X00)

SMART CARD FIFO CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

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