SEC1210 datasheet(73/218 Pages) MICROCHIP

73 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 73

SEC1110/SEC1210

10.12.1

SYNCHRONOUS INTERFACE OUTPUT

The timing diagram shows how the output behaves under different register setting for the synchronous interface when

configured as an output.

CARD_VCC_CNTL

R/W

This bit when reset disables power to the Smart Card 1 (or 2) pads.

Resetting this bit causes masking of PWR_SC1_EN (or PWR_SC2_EN)

bit in the POWER_CTL1 Register, controlling the voltage regulators to

the Smart Card pads.

This bit when set enables the PWR_SC1_EN (or PWR_SC2_EN) bit to

control the voltage regulators to the Smart Card pads. The voltage

applied is indicated by non-zero values of the PWR_SC1_EN (or

PWR_SC2_EN

) bit.

FIGURE 10-15:

SMART CARD SYNCHRONOUS OUTPUT CONFIGURATIONS

TABLE 10-12: SMART CARD SYNC ALL CONTROL REGISTER (CONTINUED)

SC_SYNC_ALL

(0X00A4- RESET=0X00)

SMART CARD ALL CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

INPUT

OUTPUT

OPEN_DRAIN = 0 FAST_OPEN_DRAIN = X

PULL_UP_EN = X, PULL_DN_EN = X

OUTPUT

OPEN_DRAIN = 1 FAST_OPEN_DRAIN = 0

PULL_UP_EN = 0, PULL_DN_EN = 0

OUTPUT

OPEN_DRAIN = 1 FAST_OPEN_DRAIN = 0

PULL_UP_EN = 1, PULL_DN_EN = 0

OUTPUT

OPEN_DRAIN = 1 FAST_OPEN_DRAIN = 1

PULL_UP_EN = 0, PULL_DN_EN = 0

OUTPUT

OPEN_DRAIN = 1 FAST_OPEN_DRAIN = 1

PULL_UP_EN = 1, PULL_DN_EN = X

(Pull up)

System Clock

High

Pull up

High

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