SEC1210 datasheet(99/218 Pages) MICROCHIP

99 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 99

SEC1110/SEC1210

For Control endpoints, each SETUP transaction starts with a DATA 0 and data toggling is then used as for Bulk end-

points until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a

DATA 1 (for a control read transfer).

11.7

NAK Handshakes

When a NAK handshake is sent by the USB controller to a IN or OUT request from the Host, the UNSUCESSFUL bit will

not be set by hardware.

11.8

Suspend

The Suspend state can be detected by the USB controller if all the USB clocks are enabled and if the USB controller is

enabled. The bit USB_SUSPEND_INT is set by hardware when an idle state is detected for more than 3 ms. This triggers

a USB interrupt, if enabled.

In order to reduce current consumption, the firmware can put the USB pads in suspend Mode, stop the clocks and put

the chip in Idle or Power-Down Mode. The Resume detection is still active.

The USB suspend Mode is entered when the firmware sets PWR_CORE_DIS0 to shutdown LDO3A regulator and then

writes to the OSC48_CTL Register. The two writes to these registers must be consecutive. If operating from external

clock then EXT_OSC_SLEEP bit is set in the second write, and if operating from the internal clock, then OSC_MODE[2] bit

is set.

The hardware shuts the clocks and the oscillator. It also powers down all the logic except for the USB subsystem, ERAM

(optional), IRAM (optional), GPIO logic. Hence the firmware must save all the CPU registers in ERAM before entering

suspend Mode. The USB PAD automatically exits from idle Mode when a wake-up event is detected on GPIO or USB

pads.

The stop of the 48 MHz clock from the oscillator should be done in the following order:

Disable all other peripherals not required during suspend Mode. Save CPU and SFR registers state in ERAM.

Disable the oscillator by writing OSC_MODE[2] as 0 in the OSC48_CTL Register or enter low power Mode by writ-

ing 000b to OSC_MODE bits (4 MHz). In case of external oscillator Mode EXT_OSC_SLEEP bit is set.

11.9

Resume

When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if

the chip is in Idle or Power-Down Mode. The USB_WU_INT bit is set by hardware when a non-idle state occurs on the

USB bus. This triggers an interrupt if enabled. This interrupt wakes up the oscillator and CPU from its idle or power-

down state and the interrupt function is then executed. The firmware will first enable the 48 MHz generation.

The firmware has to clear the USB_WU_INT bit in the USB_INT_REG Register before any other USB operation in order

to wake up the USB controller from its Suspend Mode. The USB controller is then re-activated.

11.10 Remote Wake-Up

A USB device can be allowed by the Host to send an upstream resume for Remote Wake-Up purpose. The firmware

must set the USB_REMOTE_WU_CAP bit indicating to the core that the device is remote wake-up capable. The USB con-

troller automatically responds to Set Feature and Clear Feature commands for the Remote Wake-Up capability.

If the device is in SUSPEND Mode, and the device is in low power state, the USB controller can send an upstream

Resume by setting to 1 the USB_REMOTE_WU bit in the USB_UDC_CTL Register. All clocks must be enabled first. The

UDC core ensures that the bus was idle for 6 ms before indicating Suspend. Hence the Resume would be initiated

immediately after USB_REMOET_WU bit is set. When the upstream Resume is completed, the USB_REMOTE_WU bit is

reset to 0 by hardware. The firmware should then clear the USB_WU_INT interrupt bit.

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