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SEC1210 Datasheet(PDF) 92 Page - Microchip Technology

Part # SEC1210
Description  Smart Card Bridge to USB and UART Interfaces
PDF  218 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SEC1210 Datasheet(HTML) 92 Page - Microchip Technology

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SEC1110/SEC1210
DS00001561C-page 92
 2013 - 2016 Microchip Technology Inc.
11.0
USB CONTROLLER DESCRIPTION
The SEC1110 and SEC1210 implements a USB device controller supporting 12 Mbps data transfer. In addition to the
default control Endpoint 0, it provides 5 other endpoints, which can be configured in Control, Bulk, Interrupt or Isochro-
nous modes:
• Endpoint 0: 8/16/32/64-byte buffer, default control endpoint
• Endpoints 1,2,3,4,5: 8/16/32/64 -byte buffer or buffers in ping-pong Mode.
The Digital Phase-Locked Loop (DPLL) blocks main function is to extract the USB clock and data from the USB cable.
Its main input is an external differential transceiver. The DPLL block has a built-in digital PLL that runs on a user-pro-
vided 48 MHz clock in 12 Mbps configuration. The DPLL block also extracts from the 48 MHz clock, a 12 MHz clock that
it can supply to the SIE and UBL blocks.
The D+ and D- signals on the USB lines are passed through a differential receiver (external to the UDC core) and NRZI-
formatted data is obtained from the differential receiver output. The DPLL uses this differential receiver output to extract
clock information. The DPLL block also has single-ended zero (SE0) detection logic to detect SE0 signals in the data
stream on the USB transceiver.
The clock and reset block generates a separate 12 MHz clock, by dividing the reference 48 MHz clock by 4 (for 12 Mbps
applications). The UDC core uses this 12 MHz clock, which is also provided on the application bus.
The Serial Interface Engine (SIE) block performs all front-end USB protocol functions, such as SYNC field identification,
NRZI-NRZ conversion, token packet decoding, bit stripping, bit stuffing, NRZ-NRZI conversion, CRC5 checking, and
CRC16 generation and checking. The SIE block also converts serial packets to 8-bit parallel data. The SIE block has a
built-in 1-byte buffer for buffering data during transmission and reception of IN, OUT, and setup transactions. The SIE
block interfaces to the device logic through the USB bridge layer.
The SIE runs on the 1x clock provided by the DPLL block, even though the data from the USB is received on the USB
clock. For actual packet data, the SIE assembles the bits into bytes and forwards them to the application.
The main SIE block functions include:
• SYNC field identification
• NRZI-NRZ conversion during data reception
• Token packet identification
FIGURE 11-1:
USB BLOCK DIAGRAM



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