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SEC1210 Datasheet(PDF) 77 Page - Microchip Technology

Part # SEC1210
Description  Smart Card Bridge to USB and UART Interfaces
PDF  218 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SEC1210 Datasheet(HTML) 77 Page - Microchip Technology

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 2013 - 2016 Microchip Technology Inc.
DS00001561C-page 77
SEC1110/SEC1210
3
PER_SIG_MODE
R/W
In SEC1110/SEC1210, always read as 0.
In SEC1110/SEC1210 this bit indicates the assertion time of parity
error.
0 : Parity error is signaled for one ETU, as measured by internal block
sc_clk. The actual width of parity error depends on rise/fall delays of
SCx_IO line. (default)
1 : Parity error is signaled for 1.25 ETU, as measured by internal
block sc_clk. This setting ensures, that the parity error assertion width
is independent of rise/fall time on SCx_IO line.
2
TMO_CONFIG
R/W
This bit defines the unit resolution of Timeout Timer.
0 : Timeout Timer Unit Resolution is in 1.25 milliseconds.
1 : Timeout Timer Unit Resolution is one ETU.
1
APDE
R/W
Automatic Parity-Error Deactivate Enable:
1 : Causes the ICC to be deactivated by hardware upon a non-
recoverable parity error. The device must also be in T=0 Mode for this
to occur. If the CRE bit is also 0, this will occur without performing
character repetition or signalling to the ICC.
0
CRE
R/W
Character Repeat Enable:
1 : Enables character repeat in T=0 Mode if a Parity Error is signalled
by the ICC.
TABLE 10-18: SMART CARD INTERFACE MONITOR REGISTER
SC_INTF_MON
(0X0004- RESET=0B00X10XX0)
SMART CARD INTERFACE MONITOR REGISTER
BIT
NAME
R/W
DESCRIPTION
7
FFULL
R/W
FIFO Full: indicates that the FIFO is completely full with data to be
transmitted.
6
Reserved
R
Always read as 0
5
PSNT
R/W
This pin reflects the state of the SCx_PRSNT_N pin.
4
CRMV
R/W
Card Removed:
This bit is set to 1 when a card is being removed. It is a read-only 1,
and cannot be cleared by software, as long as the debounced version
of the SCx_PRSNT_N signal is high.
When SCx_PRSNT_N goes low, this bit can be cleared by writing a 1
to it. While this bit is 1, the SC_ICR Register is held to its default
state, which holds the signals SCx_IO, SCx_CLK and SCx_RST_N
low.
3
FTH
R/W
1 : Indicates the presence of a FIFO Threshold Interrupt request.
2
RST_N
R/W
Indicates the current state of the SCx_RST_N pin.
1
IO
R/W
Indicates the current state of the SCx_IO pin.
0
CRPT
R/W
Indicates, in T=0 Mode, whether any characters needed to be
repeated to the ICC. This bit may be cleared by writing a 1 to it. This
is an indicator only.
TABLE 10-17: SMART CARD LINE CONTROL REGISTER (CONTINUED)
SC_LCR
(0X0003- RESET=0X00)
SMART CARD LINE CONTROL REGISTER
BIT
NAME
R/W
DESCRIPTION



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