SEC1210 datasheet(80/218 Pages) MICROCHIP

80 / 218 page

SEC1110/SEC1210

DS00001561C-page 80

 2013 - 2016 Microchip Technology Inc.

TABLE 10-23: SMART CARD PROTOCOL STATUS REGISTER

SC_PRS

(0X000C- RESET=0X04)

SMART CARD PROTOCOL STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

Reserved

Always read as 0

INVALID_START_STS

This bit is set when an invalid start bit received.

Invalid start bit is detected when any of the below checks fail.

• Start bit period less than 0.5 etu

• A level LOW check on SCx_IO pin at the sample time specified in

the START_WIDTH_TOL register

This bit is reset when read or when RSE bit in SC_FCR register is set.

In SEC1110/SEC1210, always read as 0.

SMB

R/W

State Machine Busy:

: Indicates that a transfer is in progress

: Indicates that no transfer is in progress (idle/finished)

PWR

R/W

This bit is forced to 0

ACTV

R/W

Activity Bit:

1 : Indicates that a character has been received since the last time

this bit was cleared by software. This bit is cleared by software, by

writing a 0 to this bit location (this is the only writable bit in this

order for this bit to detect activity, and the FRE bit does not have to

be 1.

GPH

R/W

Guard Timer Phase:

Indicates the current phase of operation for the Guard Timer:

: next reload will be from the SC_EGT Register

: next reload will be from the BGT Register

TSM

R/W

TS Mode:

Indicates the current convention: 0 = direct, 1 = inverse. Writing a 1

to the ATR bit in the Protocol Mode Register initializes this bit to 0,

and it can be manipulated using some test register features.

Otherwise, it is a read-only bit.

TSC

R/W

TS Captured:

1 : Indicates that a convention has been automatically captured from

an ATR TS byte. Writing a 1 to the ATR bit in the Protocol Mode

test register features. Otherwise, it is a read-only bit.

TABLE 10-24: SMART CARD PROTOCOL INTERRUPT PENDING REGISTER

SC_PRIP

(0X000D- RESET=0X00)

SMART CARD PROTOCOL INTERRUPT PENDING REGISTER

BIT

NAME

R/W

DESCRIPTION

GPT

R/W

1 : General Purpose Down Counter Interrupt

TSW

R/W

1 : Timeout waiting for the TS byte in ATR Mode. (Guard Timer, EGT

reload phase.)

TMO

R/W

1 : Timeout on the Timeout Timer (WWT, BWT or WTX)

CWT

R/W

1 : Timeout on the CWT Timer (CWT, or timeout waiting for the ATR

TS byte)

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