SEC1210 datasheet(48/218 Pages) MICROCHIP

48 / 218 page

SEC1110/SEC1210

DS00001561C-page 48

 2013 - 2016 Microchip Technology Inc.

10.3

General Description

The Smart Card Interface serves as the core of a Terminal, or Interface Device (IFD), which communicates with an

insertable Smart Card, also called an Integrated Circuit Card (ICC).

The Smart Card interface is a UART-like interface that supports the ISO 7816 asynchronous protocols named T=0 and

T=1. It transmits and receives serial data via the SCx_IO (x is 1 or 2) signal pin. Each byte transmitted or received is

transferred as a character with a start bit, 8 data bits, a parity bit, and an amount of Guard Time (stop bits) that depends

on the protocol used and the declared characteristics of the card.

To initiate communication with the Smart Card, the Smart Card must be inserted into the terminal device. A mechanical

or electrical sensor will detect this event, pulling the SCx_PRSNT_N(GPIO6 or GPIO19) pin low to indicate that the elec-

trical contacts are seated. The insertion of the card will cause a GPIO6 or GPIO19 Interrupt after the debounce period.

If the system is in suspend state, the GPIO transition will cause the system to be woken up first, followed by the interrupt

to the processor.

Once it is established that a Smart Card is present, firmware will use the VREG_CTL Register to apply power to the

card. Once the interface is powered, the terminal can initiate communication with the Smart Card by driving the SCx-

_RST_N pin low. There are two types of resets: a cold reset and a warm reset. The cold reset sequence is used imme-

diately after power is applied to the interface: it generates the SCx_CLK output, sets the SCx_IO pin as an input with a

weak pull-up, and keeps the SCx_RST_N pin low (its initial state) for a defined period of time after the clock starts run-

ning. The warm reset only affects the SCx_RST_N pin, which is pulled low for a defined period of time: it requires that

the interface already be powered and a steady clock be already applied to the card. Bits have been provided in the

SC_ICR Register that may be controlled by software to initiate these sequences. When either of these resets terminates

(SCx_RST_N going high) the Smart Card will return a sequence of characters called the Answer to Reset (ATR) mes-

sage as defined by ISO 7816-3. The Smart Card is required to respond to a reset sequence as shown in the cold reset

and warm reset timing diagrams (see Figure 10-10 and FIGURE 10-11: on page 62).

The first character of the ATR message, called TS, is interpreted by hardware in the SEC1110 and SEC1210, determin-

ing the bit encoding convention used by the card (direct or inverse) as defined by ISO 7816-3, which defines the polarity

and the order of the data and parity bits in the character. The TS byte, interpreted according to the convention it selects,

is placed into the FIFO, and data received from that point onward is assembled according to the selected convention

and loaded into the FIFO to be read by software.

The rest of the ATR response from the Smart Card returns the operational limits of the Smart Card. Software must inter-

pret this response and set the SEC1110 and SEC1210 runtime registers accordingly. During the ATR message, data

will be received based on a default value of the bit time, called the Elementary Time Unit (etu). Two ATR parameters

named F and D are used to define a new etu time. Once this is determined, software can program the BRG Divisor

(SC_DLM and SC_DLL) and the sampling rate for the baud rate generator accordingly. The hardware divides the

Mhzsc1_clk (typically 48 MHz) system clock, by the BRG divisor and the sampling rate to determine the etu value (bit

time). The SCx_CLK frequency is generated by dividing the sc1_clk clock by the SC_CLK_DIV DIVISOR field. Software

will also set up the Extra Guard Time Register (SC_EGT), the Block Guard Time (SC_BGT) Register and the protocol

Mode (T=0 or T=1 Mode) to set the required amount of Guard Time between character transmissions.

A negotiation phase called PPS may occur, or communication may begin immediately using the parameters provided

by the card’s ATR message. In either case, all communication after the ATR message consists of individual exchanges,

in which the IFD transmits a block of data and the ICC responds with a return message. For this reason, and because

the response time from the ICC can be too short for software intervention, software will enable both the SEC1110 and

SEC1210 transmitter and receiver at the same time, and the receiver hardware will remain inactive until the transmission

phase of the exchange has completed.

An additional stop clock feature has been provided to hold the SCx_CLK output at a particular voltage level between

exchanges, as may be allowed by the card for power savings. Clock switching is glitch free.

Hardware protocol timers, set according to default timings, will monitor the Smart Card interface during the reset/ATR

sequence for an unresponsive or defective card, based on the EMV, ISO and PC/SC timing requirements. If the ATR

response is not received within the given time, or does not obey the required timings, a Timer Interrupt will result. The

software can then take corrective action or initiate the deactivation sequence to stop and power-down the card.

After the ATR sequence, the same set of hardware timers are used, based on ATR parameters EGT, CWT, BWT, and/or

WWT, to monitor timings for the subsequent data exchanges.

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