SEC1210 datasheet(63/218 Pages) MICROCHIP

63 / 218 page

 2013 - 2016 Microchip Technology Inc.

DS00001561C-page 63

SEC1110/SEC1210

To anticipate the ATR sequence, the controller is placed by software into a special Mode called ATR. In the ATR Mode,

two of the timers are in a special Mode to validate the timing of the sequence. Figure 10-10 shows the sequence of

events in a Cold Reset, where power has been removed from the card. Figure 10-11 shows the sequence of events in

a Warm Reset, where power is maintained, but a new SCx_RST_N pulse is applied to reset the card.

In preparing for the ATR sequence, the software must establish the default etu time: the equivalent of TA1=0x11, or 372

periods of the selected SCx_CLK frequency.

At the beginning of the sequence, the two reload registers of the Guard Timer determine the duration of the Reset pulse

and measure the response time from the Smart Card to enforce a valid delay. After the first character, the CWT Timer

starts, and counts the maximum amount of time the card is allowed to spend between characters. When the CWT Timer

expires, an interrupt (CWT) is sent to the software, which can then read the message from the SC_FIFO. This event will

also set the FIFO Threshold Interrupt active. Software will be able to parse the message and determine whether it is

complete.

Software may, rather than using the CWT Timer for this purpose, set thresholds for the SC_FIFO such that it is period-

ically interrupted either by the individual characters or by larger expected fields. The CWT Timer will still be useful as

an error indication.

The first byte (TS) is interpreted by hardware. One of two values is allowed, which from that point onward determines

the convention used by the card. The possible conventions used are listed below. L means a bit time with the SCx_IO

pin held low, and H means a bit time with the SCx_IO pin held high.

• Direct Convention, which is signaled by the TS bit sequence LHHLHHHLLHHH. In this convention, bits of a char-

acter are sent least-significant bit first, 0 bits in the data field are represented by the Low state, and a true Even

parity is used. The first byte will always appear in the SC_FIFO, in Direct/Indirect convention as was seen on the

SCx_IO pin. Subsequent bytes will be decoded as per the convention and loaded into the SC_FIFO. The first byte

will appear as 0x3B in the SC_FIFO in Direct convention.

• Inverse Convention, which is signalled by the TS bit sequence LHHLLLLLLHHH. In this convention, bits of a char-

acter are sent most-significant bit first, 0 bits in the data field are represented by the High state, and an inverted

Even parity bit is used (appearing as a parity error to any circuit reading it according to the Direct convention). This

byte will appear as 0x03 in the SC_FIFO.

• The Direct or Inverse Convention will be selected automatically by hardware after receiving the TS byte after a ris-

ing edge on the SCx_RST_N signal. This setting will be reported in the TSM bit of the Protocol Status Register,

and will be used to interpret all characters until the next SCx_RST_N pulse. If any TS value other than the two

above is seen, the Receiver will be disabled, and the CV bit (Code Violation) will be set in the PRIP Register to

indicate the error. If a FIFO threshold larger than one byte was selected, the eventual CWT Timer Interrupt will

both set the FIFO Threshold Interrupt and alert the software to look at the error flag.

While power is not applied to the card, the terminal is required to hold the SCx_RST_N, SCx_CLK and SCx_IO pins low

(not floating). When power is first applied to the card (a Cold Reset, shown in FIGURE 10-10: ATR Sequence, Cold

Reset on page 62), the SCx_RST_N pin must be held low until SCx_CLK begins running. SCx_IO must rise to its idle

state (high) after power has been applied, and no later than 200 cycles of SCx_CLK. The SCx_RST_N pin must then be

set high between 108 and 120 default etu times after the clock starts.

When the card has already been initialized from a Cold Reset, it may be reset without removing power (Warm Reset,

as shown in FIGURE 10-11: ATR Sequence, Warm Reset on page 62). In this case, the clock keeps running, SCx_IO

should remain high, and the time range of 108 to 120 default etu times applies to the width of the SCx_RST_N pulse.

10.9.4

GUARD TIME ALGORITHM

A special case occurs under some circumstances, in which software thinks that an exchange is finished, but the card

does not, and keeps transmitting characters. One such case is when a parity error occurs in a T=1 message. The

SC_FIFO stops receiving characters after the faulty one (for diagnostic purposes, to indicate the character with the

error), and signals to software an End of Message with an error.

In this circumstance, it is necessary that any transmission commanded by the software (e.g., the packet complaining

about the parity error) must wait until the card is finished transmitting. However, if the card is misbehaving and does not

stop transmitting, then software must be informed of this error so that the card can be deactivated. The Guard Time

algorithm hardware serves both of these purposes.

A specific error flag is provided (TF), and a timing register (GSR), to support this feature. The feature is not optional,

and so it cannot be disabled.

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