SEC1210 datasheet(86/218 Pages) MICROCHIP

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SEC1110/SEC1210

DS00001561C-page 86

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• T=0 Mode: ATR=0 and TE1=0. In this Mode, character framing and parity handling are as per the T=0 protocol.

The Receiver waits until a message has been transmitted before it becomes active.

• T=1 Mode: ATR=0 and TE1=1. In this Mode, character framing and parity handling are as per the T=1 protocol.

The Receiver waits until a message has been transmitted before it becomes active.

The OSME and ISME bits are mutually exclusive: only one of them may be set to 1, and neither may be set to 1 without

the TE1 bit also being set to 0 and the ATR bit set to 0.

TABLE 10-41: SMART CARD PROTOCOL MODE REGISTER

SC_PRM

(0X001E- RESET=0X00)

SMART CARD REGISTER

BIT

NAME

R/W

DESCRIPTION

7:5

Reserved

Always read as 0

ISME

R/W

1 : Indicates that the Incoming Filter State Machine is enabled. The

TE1

bit and ATR bit must also be set to 0.

OSME

R/W

1 : Indicates that the Outgoing Filter State Machine is enabled. The

TE1

bit and ATR bit must also be set to 0.

Reserved

Always read as 0

TE1

R/W

0 : Indicates that T=0 character framing is being used, either in T=0

protocol communication or receiving the ATR message.

1 : Indicates that the T=1 protocol is being used. This bit may not be

set to 1 with any of bits ATR, OSME or ISME also set to 1.

ATR

R/W

Answer to Reset Mode:

1 : Indicates that a Reset sequence is to be presented, expecting a

response from the card. The TE1 bit must also be 0 in this Mode.

Writing a 1 to this bit also clears the TSC and TSM bits in the Protocol

Status Register, which causes the first byte received to be interpreted

by hardware as the TS byte, setting the bit encoding convention

based on what is received.

ATR

bit in SC_PRM Register should not be set once the ATR from the

card is received.

TABLE 10-42: SMART CARD TIMER CONTROL REGISTER

SC_TCTL

(0X001F- RESET=0X00)

SMART CARD TIMER CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

RSG

R/W

Reset Guard Timer:

This bit always reads as 0. Writing a 1 to this bit clears the ENG bit in

the Interface Control Register to 0, and removes any pending interrupt

request from the Guard Timer. (The ENG bit, which enables the Guard

Timer, is in the Interface Control Register so that the Guard Timer

may be started atomically with the presentation of SC_RST_N and

SC_CLK to the Smart Card.)

6:5

Reserved

Always read as 0

RSC

R/W

Resets the CWT Timer:

This bit always reads as 0. Writing a 1 to this bit clears the ENC bit to

0, and removes any pending interrupt request from the CWT Timer.

ENC

R/W

Writing 1 enables the CWT Timer to begin counting at the next

triggering event.

Writing 0 has no effect: to clear this bit, write 1 to the RSC bit in the

Timer Control Register. This bit is cleared by hardware action in order

to stop the timer.

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