SEC1210 datasheet(33/218 Pages) MICROCHIP

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DS00001561C-page 33

SEC1110/SEC1210

9.1.11

TIMER MODE REGISTER – TMOD

The TMOD Register is used in configuration of the R8051XC2 Timer 0 and Timer 1.

TABLE 9-14:

TIMER MODE REGISTER

TMOD

(SFR 0X89 - RESET=0X00)

TIMER MODE REGISTER

BIT

NAME

R/W

DESCRIPTION

gate

R/W

Timer 1 Gate Control:

If set, enables external gate control (pin int(1)) for Counter 1. When

int(1) is high, and tr1 bit is set, the Counter 1 is incremented every

falling edge on the t1 input pin.

c/t

R/W

Timer 1 Counter/Timer Select:

Selects the timer or counter operation. When set to 1, a counter

operation is performed; when cleared to 0, the Timer/Counter 1 will

function as a timer.

R/W

Timer 1 Mode:

Selects mode for Timer/Counter 1, as shown in Table 9-15 below.

4m0

gate

R/W

Timer 0 Gate Control:

If set, enables external gate control (pin int(0)) for Counter 0. When

int(0) is high, and tr0 bit is set, the Counter 0 is incremented every

falling edge on the t0 input pin

c/t

R/W

Timer 0 Counter/Timer Select:

Selects the timer or counter operation. When set to 1, a counter

operation is performed; when cleared to 0, the Timer/Counter 0 will

function as a timer.

R/W

Timer 0 Mode:

Selects the mode for Timer/Counter 0, as shown in Table 9-15 below.

0m0

TABLE 9-15:

TIMER/COUNTER MODES

MODE

FUNCTION

Mode 0

13-bit Counter/Timer, with 5 lower bits in the TL0 (TL1) Register and 8 bits

in TH0 (TH1) Register (for Timer 0 or Timer 1, respectively). Note, that

unlike in the 80C51, the 3 high-order bits of TL0 (TL1) are zeroed

whenever Mode 0 is enabled.

Mode 1

16-bit Counter/Timer

Mode 2

8-bit auto-reload counter/timer. The reload value is kept in TH0 (TH1),

while TL0 (TL1) is incremented every machine cycle. When TL0 (TL1)

overflows, a value from TH0 (TH1) is copied to TL0 (TL1).

Mode 3

For Timer 1: Timer 1 is stopped.

For Timer 0: Timer 0 acts as two independent 8-bit timers / counters – TL0,

TH0.

• TL0 uses the Timer 0 control bits and sets the tf0 flag on overflow.

• TH0 operates as the timer, which is enabled by the tr1 bit and sets the

tf1

flag on overflow.

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