| Electronic Components Datasheet Search |
|
SEC1210 Datasheet(PDF) 18 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
SEC1210 Datasheet(HTML) 18 Page - Microchip Technology |
|
18 / 218 page ![]() SEC1110/SEC1210 DS00001561C-page 18 2013 - 2016 Microchip Technology Inc. Note 6-1 The Smart Card1 and Smart Card2 power supply output is powered down at reset state. Note 6-2 The Smart Card1 and Smart Card2 power supply output requires an external 1.0 F capacitor. Note 6-3 Internal voltage regulator output for USB, GPIO 3.3 V IO Supply. This pin requires an external 1.0 F capacitor. Note 6-4 A weak pull down is present on the TEST, JTAG_CLK, and JTAG_TDI pads. If JTAG is connected, and this pad is pulled high, then the reset state of the pins 8 (JTAG_TMS), 13(JTAG_CLK), 14(JTAG_TDO), and 15(JTAG_TDI) functions in JTAG Mode. The weak pull-down can be disabled after reset release by software. Note 6-5 RESET_N is an analog input, which when low, powers down all internal voltage regulators and the pads are in high impedance state. The pads function as input, including pull-ups pull-downs functionality after internal 3.3V power (VDD33) is good. Note 6-6 The TEST, JTAG_CLK, and JTAG_TDI/GPIO[19] values at internal power on reset release (after RESET_N release) is captured in the chip to enter various functional or test modes. Note 6-7 Smart Card2 power supply output is powered down at reset state. Note 6-8 A weak pull-down is present on TEST, JTAG_CLK, and JTAG_TDI pads if JTAG is connected, and this pad is pulled high. The reset state of the pins 10(JTAG_TMS), 19(JTAG_CLK), 20(JTAG_TDO), and 21(JTAG_TDI) function in JTAG Mode. The weak pull-down can be disabled after reset release by software. Note 6-9 The LCD regulator LDO4 and Smart Card2 output is powered down at reset state. 12 SPI1_CLK/CTS GPIO pin for SPI1 clock Z 13 SPI1_CE/RTS GPIO pin for SPI1 chip enable Z 14 SPI1_MOSI/TXD GPIO pin for SPI1 data Z 15 TEST Test mode pin Z PD Note 6-8 Yes Note 6-6 16 USB_DM USB D- Z 17 USB_DP USB D+ Z 18 VDD33 Note 6-3 ANALOG 19 JTAG_CLK JTAG clock pin Z PD Note 6-8 Yes Note 6-6 20 SC_LED_ACT_N/JTAG_TDO GPIO output for Smart Card1 LED Z 21 SC2+PRSNT_N/JTAG_TDI GPIO input for Smart Card1 presence detect. Z PD Note 6-8 Yes Note 6-6 22 RESET_N Reset input Z ANALOG Note 6-5 23 SC2_IO Smart Card2 IO pin Z 24 SC2_CLK Smart Card2 CLK pin Z - VSS Package ground ANALOG TABLE 6-4: SEC1210 QFN 24-PIN RESET STATES Reset State Pin Pin Name Function Output PU/PD Input |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |