SEC1210 datasheet(82/218 Pages) MICROCHIP

82 / 218 page

SEC1110/SEC1210

DS00001561C-page 82

 2013 - 2016 Microchip Technology Inc.

TABLE 10-26: SMART CARD TIMER STATUS REGISTER

SC_TMS

(0X000F- RESET=0X10)

SMART CARD TIMER STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

7:5

Reserved

Always read as 0

GS_MAX_TIMEOUT

This bit if set indicates that the maximum guard spacing timeout has

happened.

TORUN

1 : Indicates that the Timeout Timer has been triggered and is running

Reserved

Always read as 0

CRUN

1 : Indicates that the CWT Timer has been triggered and is running

GRUN

1 : Indicates that the Guard Timer has been triggered and is running

TABLE 10-27: SMART CARD BAUD DIVISOR LSB REGISTER

SC_DLL

(0X0010- RESET=0X01)

SMART CARD BAUD DIVISOR LSB REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

BAUD_DIV_7_0

R/W

These are the lower 8 bits of the 16 bit baud rate divisor. The most

significant 8 bits are held in the SC_DLM Register.

The baud rate divisor, with the Sampling field of the CLK Register,

divides the etu rate from the sc1_clk/sc2_clk input clock from the

CLK_PWR block.

TABLE 10-28: SMART CARD BAUD DIVISOR MSB REGISTER

SC_DLM

(0X0011- RESET=0X00)

SMART CARD BAUD DIVISOR MSB REGISTER

BIT

NAME

R/W

DESCRIPTION

7:0

BAUD_DIV_15_8

R/W

These are the most significant 8 bits of the 16 bit baud rate divisor.

The least significant 8 bits are held in the SC_DLL Register.

The baud rate divisor, with the Sampling field of the CLK Register,

divides the etu rate from the sc1_clk/sc2_clk input clock from the

CLK_PWR block.

TABLE 10-29: SMART CARD FIFO CONTROL REGISTER

SC_FCR

(0X0012- RESET=0X00)

SMART CARD FIFO CONTROL REGISTER

BIT

NAME

R/W

DESCRIPTION

7:6

Reserved

Always read as 0

RFS

Receiver FIFO Status:

This bit indicates whether the Receiver is actively prepared to place

characters into the FIFO. It may not match the FRE bit, if the Receiver

is still waiting for a trigger to begin (e.g., waiting for transmission to

complete).

RSS

Receiver Sampling Status:

This bit indicates whether the Receiver is actively sampling for

characters. It may not match the RSE bit, if the Receiver is still waiting

for a trigger to begin. For example, in ATR Mode, it may not yet be

active, pending a rising edge on the SCx_RST_N pin.

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