FDC37M607 datasheet(112/182 Pages) SMSC

112 / 182 page

112

Stop Cycle Control

Once all IRQ/Data Frames have completed the

Host Controller will terminate IRQSER activity

by initiating a Stop Frame.

Only the Host

Controller can initiate the Stop Frame. A Stop

Frame is indicated when the IRQSER is low for

two or three clocks.

If the Stop Frame’s low

time is two clocks then the next IRQSER Cycle’s

sampled mode is the Quiet mode; and any

IRQSER device may initiate a Start Frame in

the second clock or more after the rising edge

of the Stop Frame’s pulse. If the Stop Frame’s

low time is three clocks then the next IRQSER

Cycle’s sampled mode is the Continuos mode;

and only the Host Controller may initiate a Start

Frame in the second clock or more after the

rising edge of the Stop Frame’s pulse.

Latency

Latency for IRQ/Data updates over the IRQSER

bus in bridge-less systems with the minimum

IRQ/Data Frames of seventeen, will range up to

96 clocks (3.84

µS with a 25 MHz PCI Bus or

2.88

µS with a 33 MHz PCI Bus). If one or more

PCI to PCI Bridge is added to a system, the

latency

for

IRQ/Data

updates

from

the

secondary or tertiary buses will be a few clocks

longer

for

synchronous

buses,

and

approximately double for asynchronous buses.

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential

implementation issue related to IRQ latency.

IRQ latency could cause an EOI or ISR Read to

precede an IRQ transition that it should have

followed. This could cause a system fault. The

host

interrupt

controller

responsible

for

ensuring that these latency issues are mitigated.

The recommended solution is to delay EOIs and

ISR Reads to the interrupt controller by the

same amount as the IRQSER Cycle latency in

order to ensure that these events do not occur

out of order.

AC/DC Specification Issue

All

IRQSER

agents

must

drive

sample

IRQSER synchronously related to the rising

edge of

PCI bus clock. IRQSER (SIRQ)

uses the electrical specification of PCI bus.

Electrical

parameters

will

PCI

specification, section 4, sustained tri-state.

Reset and Initialization

The IRQSER bus uses RESET_DRV as its reset

signal. The IRQSER pin is tri-stated by all

agents while RESET_DRV is active. With reset,

IRQSER Slaves are put into the (continuous)

IDLE mode. The Host Controller is responsible

for starting the initial IRQSER Cycle to collect

system’s IRQ/Data default values. The system

then follows with the Continuous/Quiet mode

protocol

(Stop

Frame

pulse

width)

for

subsequent

IRQSER

Cycles.

Host

Controller’s responsibility to provide the default

values to 8259’s and other system logic before

the first IRQSER Cycle is performed.

For

IRQSER system suspend, insertion, or removal

application,

the

Host

controller

should

programmed into Continuous (IDLE) mode first.

This is to guarantee IRQSER bus is in IDLE

state before the system configuration changes.

FDC37M607 Datasheet(PDF) 112 Page - SMSC Corporation

FDC37M607 Datasheet(HTML) 112 Page - SMSC Corporation

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