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TMS320C80GF Datasheet(PDF) 33 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MP opcode summary Table 4 through Table 6 show the opcode formats for the MP. Table 7 summarizes the master processor instruction set. Table 4. Short-Immediate Opcodes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 illop0 Dest Source 0 0 0 0 0 0 0 Unsigned Immediate trap – – – – E – – – – – 0 0 0 0 0 0 1 Unsigned Trap Number cmnd – – – – – – – – – – 0 0 0 0 0 1 0 Unsigned Immediate rdcr Dest – – – – – 0 0 0 0 1 0 0 Unsigned Control Register Number swcr Dest Source 0 00 0101 Unsigned Control Register Number brcr – – – – – – – – – – 0 0 0 0 1 1 0 Unsigned Control Register Number shift.dz Dest Source 0 0 0 1 0 0 0 – – – i n Endmask Rotate shift.dm Dest Source 0 00 1001 – –– i n Endmask Rotate shift.ds Dest Source 0 00 1010 – –– i n Endmask Rotate shift.ez Dest Source 0 00 1011 – –– i n Endmask Rotate shift.em Dest Source 0 00 1100 – –– i n Endmask Rotate shift.es Dest Source 0 00 1101 – –– i n Endmask Rotate shift.iz Dest Source 0 00 1110 – –– i n Endmask Rotate shift.im Dest Source 0 00 1111 – –– i n Endmask Rotate and.tt Dest Source2 0 0 1 0 0 0 1 Unsigned Immediate and.tf Dest Source2 0 01 0010 Unsigned Immediate and.ft Dest Source2 0 01 0100 Unsigned Immediate xor Dest Source2 0 01 0110 Unsigned Immediate or.tt Dest Source2 0 01 0111 Unsigned Immediate and.ff Dest Source2 0 01 1000 Unsigned Immediate xnor Dest Source2 0 01 1001 Unsigned Immediate or.tf Dest Source2 0 01 1011 Unsigned Immediate or.ft Dest Source2 0 01 1101 Unsigned Immediate or.ff Dest Source2 0 01 1110 Unsigned Immediate ld Dest Base 0 1 0 0 M SZ Signed Offset ld.u Dest Base 0 10 1 M SZ Signed Offset st Source Base 0 11 0 M SZ Signed Offset dcache – – – – F Source2 0 1 1 1 M 0 0 Signed Offset bsr Link – – – – – 1 0 0 0 0 0 A Signed Offset jsr Link Base 1 00 010 A Signed Offset bbz BITNUM Source 1 0 0 1 0 0 A Signed Offset bbo BITNUM Source 1 00 101 A Signed Offset bcnd Cond Source 1 00 110 A Signed Offset cmp Dest Source2 1 0 1 0 0 0 0 Signed Immediate add Dest Source2 1 0 1 1 0 0 U Signed Immediate sub Dest Source2 1 01 101 U Signed Immediate – Reserved bit (code as 0) M Modify, write modified address back to register A Annul delay slot instruction if branch taken n Rotate sense for shifting E Emulation trap bit SZ Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword) F Clear present flags U Unsigned form i Invert endmask |
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