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TMS320C80GF Datasheet(PDF) 43 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pipeline registers (continued) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76 54 3210 pc PC (29-Bit Doubleword Address) – G L G – Global Interrupt Enable L – Loop Inhibit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76 54 3210 ipa 32-Bit Copy of the Previous pc Register Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76 54 3210 ipe 32-Bit Copy of the Previous ipa Register Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76 54 3210 iprs 29-Bit Doubleword Return Address – – – Figure 30. Pipeline Registers interrupt registers The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag (intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving from left to right on intflg. Figure 31 shows the PP-interrupt register format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 inten r r r r E E E E – – – E E E E – – E – – – – – – – – – – – – – W P P 3 M S G P P 2 M S G P P 1 M S G P P 0 M S G M P M S G P T E N D P T E R R P T Q T A S K 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 intflg r r r r I I I I – – – I I I I – – I – – – – – – – – – – – – – – r E W PPnMSG Reserved (write as 0) Enable Interrupt Write Mode 0 – writing 1 clears intflg 1 – writing 1 sets intflg PPn message Interrupt MPMSG PTEND PTERR PTQ TASK MP Message Interrupt Packet Transfer Complete Packet-Transfer Error Packet Transfer Queued MP Task Interrupt Figure 31. PP-Interrupt Registers |
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