TMS320C80GF datasheet(50/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PP address-unit architecture (continued)

From Global

Destination Bus

Offset

To Global

Source Bus

From Global

Destination Bus

To Global

Source Bus

sp = a6 (local)

sp = a14 (global)

a0 – a4

(a7 = 0)

x0 – x2

a8 – a12

(a15 = 0)

x8 – x10

Preindex / Postindex

Multiplexer

Scale

Preindex / Postindex

Local-Address Port

Offset

pba dba

Index Multiplexer

Data Size

PP-Relative

Multiplexer

Index Scaler

pba, dba

Index Multiplexer

32-Bit Adder / Subtracter Unit

Preindex / Postindex

Scale

Data Size

PP-Relative

Multiplexer

Index Scaler

Preindex / Postindex

Multiplexer

Global-Address Port

32-Bit Adder / Subtracter Unit

Figure 44. Address-Unit Architecture

PP instruction set

PP instructions are represented by algebraic expressions for the operations performed in parallel by the

multiplier, ALU, global-address unit, and local-address unit. The expressions use the || symbol to indicate

operations that are to be performed in parallel. The PP ALU operator syntax is shown in Table 9. The data unit

operations (multiplier and ALU) are summarized in Table 10 and the parallel transfers (global and local) are

summarized in Table 11.

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